{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T08:22:26Z","timestamp":1729671746134,"version":"3.28.0"},"reference-count":35,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,4]]},"DOI":"10.1109\/ddecs.2019.8724659","type":"proceedings-article","created":{"date-parts":[[2019,5,30]],"date-time":"2019-05-30T18:52:12Z","timestamp":1559242332000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["Low Latency Hardware-Accelerated Dynamic Memory Manager for Hard Real-Time and Mixed-Criticality Systems"],"prefix":"10.1109","author":[{"given":"Lukas","family":"Kohutka","sequence":"first","affiliation":[]},{"given":"Lukas","family":"Nagy","sequence":"additional","affiliation":[]},{"given":"Viera","family":"Stopjakova","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW.2010.5470740"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1007\/BF00263294"},{"key":"ref31","doi-asserted-by":"crossref","first-page":"26","DOI":"10.1145\/301589.286864","article-title":"The memory fragmentation problem: solved?","volume":"34","author":"johnstone","year":"1998","journal-title":"SIGPLAN Not"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1093\/comjnl\/bxh101"},{"key":"ref35","first-page":"21","article-title":"Efficient systolic arrays for matrix multiplication","volume":"iii","author":"klass","year":"1991","journal-title":"Proc Int Conf Parallel Processing Austin Tex"},{"key":"ref34","article-title":"Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches","author":"moon","year":"2000","journal-title":"IEEE Transactions on Computers"},{"key":"ref10","article-title":"Utilization of FPGAs in Real-Time and Embedded Systems","author":"pohronsk\u00e1","year":"2009","journal-title":"Proceedings in Informatics and Information Technologies Student Research Conference"},{"article-title":"Hardware Co-Processor for the OReK Real-Time Executive","year":"2010","author":"ferreira","key":"ref11"},{"article-title":"RTOS Hardware Coprocessor Implementation in VHDL","year":"2009","author":"ferreira","key":"ref12"},{"key":"ref13","first-page":"207","article-title":"Sorensen: HartOS - a Hardware Implemented RTOS for Hard Real-time Applications","author":"lange","year":"2012"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.14257\/astl.2013.31.35"},{"article-title":"Real-Time Scheduling with Hardware Data Structures","year":"2010","author":"bloom","key":"ref15"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/SPL.2012.6211775"},{"key":"ref17","article-title":"Real-Time Systems and Programming Languages","author":"burns","year":"2001","journal-title":"Addison Wesley"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2014.2315637"},{"key":"ref19","article-title":"Real-Time Scheduling Co-Processor in Hardware for Single and Multiprocessor Systems","author":"starner","year":"1996","journal-title":"Proceedings of the EUROMICRO Conference"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/359436.359453"},{"key":"ref4","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4614-0676-1","article-title":"Hard Real-Time Computing Systems: Predictable Scheduling Algorithms and Applications","author":"buttazzo","year":"2011"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/65979.65981"},{"key":"ref3","article-title":"Tutorial hard real-time systems","author":"stankovic","year":"1988","journal-title":"IEEE Computer Society Press"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1201\/9781420011746"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1016\/S1477-8424(04)00021-1"},{"key":"ref5","article-title":"Embedded Systems Design","author":"heath","year":"2003","journal-title":"Newnes"},{"article-title":"Embedded System Design: Embedded Systems Foundations of Cyber-physical Systems","year":"2010","author":"marwedel","key":"ref8"},{"key":"ref7","article-title":"Real-time Systems Specification, Verification and Analysis","author":"joseph","year":"2001","journal-title":"Prentice Hall International"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1117\/12.948443"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/978-0-387-39362-9_21"},{"journal-title":"Real Time Theory and Practice","year":"2008","author":"mall","key":"ref1"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/CANDAR.2013.110"},{"key":"ref22","first-page":"907","article-title":"Algorithms for compile-time memory optimization","author":"gergov","year":"1999","journal-title":"Proceedings of the tenth annual ACM-SIAM symposium on Discrete algorithms SODA &#x2019;99"},{"key":"ref21","article-title":"Real-Time Scheduling in Heterogeneous Dual-core Architectures","author":"kim","year":"2006","journal-title":"Proc 12th Int'l Conf Parallel and Distributed Systems"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/PDCAT.2011.18"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/173262.155108"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/362375.362392"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2009.154"}],"event":{"name":"2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","start":{"date-parts":[[2019,4,24]]},"location":"Cluj-Napoca, Romania","end":{"date-parts":[[2019,4,26]]}},"container-title":["2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits &amp; Systems (DDECS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8718445\/8724630\/08724659.pdf?arnumber=8724659","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,9,16]],"date-time":"2023-09-16T22:23:11Z","timestamp":1694902991000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8724659\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,4]]},"references-count":35,"URL":"https:\/\/doi.org\/10.1109\/ddecs.2019.8724659","relation":{},"subject":[],"published":{"date-parts":[[2019,4]]}}}