{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T04:20:29Z","timestamp":1725596429752},"reference-count":13,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,4]]},"DOI":"10.1109\/ddecs.2019.8724661","type":"proceedings-article","created":{"date-parts":[[2019,5,30]],"date-time":"2019-05-30T22:52:12Z","timestamp":1559256732000},"page":"1-4","source":"Crossref","is-referenced-by-count":1,"title":["Nonlinear Compression Codes Used In IC Testing"],"prefix":"10.1109","author":[{"given":"Ondrej","family":"Novak","sequence":"first","affiliation":[]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1109\/ETS.2017.7968244"},{"year":"1989","author":"pless","journal-title":"Introduction to the Theory of Error-Correcting Codes","key":"ref11"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1109\/TCAD.2004.826558"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1109\/43.7806"},{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1109\/ATS.2014.67"},{"key":"ref3","first-page":"214","article-title":"Pseudoexhaustive Test Pattern Generation for Structured Digital Circuits","author":"golan","year":"1986","journal-title":"Proc IX International Conference on Fault Tolerant Systems and Diagnostics FTSD 9"},{"year":"2018","key":"ref6"},{"key":"ref5","first-page":"260","article-title":"Reducing Test Application Time for Full Scan Embedded Cores","year":"1999","journal-title":"Proc Int Symp Fault Tolerant Computing"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1145\/288548.288563"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1109\/ICCAD.2003.159776"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1109\/ATS.2002.1181709"},{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1109\/DFT.2014.6962079"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1109\/TC.2006.31"}],"event":{"name":"2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","start":{"date-parts":[[2019,4,24]]},"location":"Cluj-Napoca, Romania","end":{"date-parts":[[2019,4,26]]}},"container-title":["2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits &amp; Systems (DDECS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8718445\/8724630\/08724661.pdf?arnumber=8724661","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,19]],"date-time":"2022-07-19T20:21:45Z","timestamp":1658262105000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8724661\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,4]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/ddecs.2019.8724661","relation":{},"subject":[],"published":{"date-parts":[[2019,4]]}}}