{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,11]],"date-time":"2026-05-11T11:21:39Z","timestamp":1778498499765,"version":"3.51.4"},"reference-count":12,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,4,7]],"date-time":"2021-04-07T00:00:00Z","timestamp":1617753600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,4,7]],"date-time":"2021-04-07T00:00:00Z","timestamp":1617753600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,4,7]],"date-time":"2021-04-07T00:00:00Z","timestamp":1617753600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,4,7]]},"DOI":"10.1109\/ddecs52668.2021.9417052","type":"proceedings-article","created":{"date-parts":[[2021,4,30]],"date-time":"2021-04-30T20:25:43Z","timestamp":1619814343000},"page":"99-104","source":"Crossref","is-referenced-by-count":47,"title":["PolyAdd: Polynomial Formal Verification of Adder Circuits"],"prefix":"10.1109","author":[{"given":"Rolf","family":"Drechsler","sequence":"first","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1995.250005"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/12.73590"},{"key":"ref10","author":"becker","year":"2005","journal-title":"Technische Informatik - Eine Einfu?hrung"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1986.1676819"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1137\/1.9780898719789"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1997.599468"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/EDTC.1996.494346"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1990.114826"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-2892-7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-57685-5"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/s100090100056"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/b105236"}],"event":{"name":"2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","location":"Vienna, Austria","start":{"date-parts":[[2021,4,7]]},"end":{"date-parts":[[2021,4,9]]}},"container-title":["2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9417028\/9417018\/09417052.pdf?arnumber=9417052","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T15:41:13Z","timestamp":1652197273000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9417052\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,4,7]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/ddecs52668.2021.9417052","relation":{},"subject":[],"published":{"date-parts":[[2021,4,7]]}}}