{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T14:58:55Z","timestamp":1730213935156,"version":"3.28.0"},"reference-count":35,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,4,6]],"date-time":"2022-04-06T00:00:00Z","timestamp":1649203200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,4,6]],"date-time":"2022-04-06T00:00:00Z","timestamp":1649203200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,4,6]]},"DOI":"10.1109\/ddecs54261.2022.9770145","type":"proceedings-article","created":{"date-parts":[[2022,5,9]],"date-time":"2022-05-09T16:06:40Z","timestamp":1652112400000},"page":"38-43","source":"Crossref","is-referenced-by-count":0,"title":["A Design Space Exploration Framework for Memristor-Based Crossbar Architecture"],"prefix":"10.1109","author":[{"given":"Mario","family":"Barbareschi","sequence":"first","affiliation":[{"name":"University of Naples Federico II,Department of Electrical Engineering and Information Technology,Naples,Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alberto","family":"Bosio","sequence":"additional","affiliation":[{"name":"Univ Lyon,Ecully,France,69130"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ian","family":"O'Connor","sequence":"additional","affiliation":[{"name":"Univ Lyon,Ecully,France,69130"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Petr","family":"Fiser","sequence":"additional","affiliation":[{"name":"Czech Technical University in Prague,Czech Republic"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marcello","family":"Traiola","sequence":"additional","affiliation":[{"name":"University of Rennes"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","article-title":"IWLS 2005 benchmarks","author":"albrecht","year":"2005","journal-title":"Tech Rep"},{"key":"ref32","article-title":"The EPFL combinational benchmark suite","author":"amaru","year":"2016","journal-title":"Integrated Systems Laboratory EPFL Lausanne Switzerland Tech Rep"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/54.867894"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1989.100747"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1038\/nature08940"},{"year":"0","key":"ref34","article-title":"Freepdk45"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2016.7753567"},{"year":"0","key":"ref11","article-title":"Xbargen website"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TNNLS.2014.2334701"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744795"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2282132"},{"key":"ref15","first-page":"97","article-title":"Synthesis of memristive circuits based on stateful IMPLY gates using an evolutionary algorithm with a correction function","author":"wang","year":"2016","journal-title":"2016 IEEE\/ACM International Symposium on Nanoscale Architectures (NANOARCH)"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2014.7001393"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2014.2357292"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/IDT.2014.7038601"},{"key":"ref19","first-page":"948","article-title":"Fast Logic Synthesis for RRAM-Based in-Memory Computing Using Majority-Inverter Graphs","author":"saeideh shirinzadeh","year":"2016","journal-title":"Design Automation Test in Europe Conference Exhibition (DATE)"},{"key":"ref28","article-title":"IWLS’93 Benchmark Set: Version 4.0","author":"mcelvain","year":"1993","journal-title":"Tech Rep"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1002\/adma.200900375"},{"key":"ref27","article-title":"Logic synthesis and optimization benchmarks user guide: Version 3.0","author":"yang","year":"1991","journal-title":"MCNC Technical Report Tech Rep"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCT.1971.1083337"},{"key":"ref6","article-title":"A functional hybrid memristor crossbar-array\/cmos system for data storage and neuromorphic applications","volume":"12","author":"kim","year":"2011","journal-title":"Nano Letters"},{"key":"ref29","first-page":"677","article-title":"A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran","author":"brglez","year":"1985","journal-title":"IEEE International Symposium Circuits and Systems (ISCAS’85)"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/NanoArch.2013.6623028"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2015.7357122"},{"key":"ref7","first-page":"1718","article-title":"Memristor based computation-in-memory architecture for data-intensive applications","author":"hamdioui","year":"2015","journal-title":"2015 Design Automation Test in Europe Conference Exhibition (DATE)"},{"key":"ref2","first-page":"421","article-title":"Chips 2020: A guide to the future of nanoelectronics","author":"hoefflinger","year":"2012","journal-title":"The Frontiers Collection Heidelberg"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2018.2869760"},{"year":"2013","key":"ref1","article-title":"ITRS 2013 report"},{"key":"ref20","first-page":"43","article-title":"Synthesizing HDL to memristor technology: A generic framework","author":"nguyen","year":"2016","journal-title":"2016 IEEE\/ACM International Symposium on Nanoscale Architectures (NANOARCH)"},{"journal-title":"CMOS VLSI Design A Circuits and Systems Perspective","year":"2010","author":"weste","key":"ref22"},{"key":"ref21","first-page":"1","article-title":"A mapping methodology of boolean logic circuits on memristor crossbar","volume":"pp","author":"xie","year":"2017","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"article-title":"ABC: A system for sequential synthesis and verification","year":"2012","author":"mishchenko","key":"ref24"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1007\/s00339-004-3149-1"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2017.12.009"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4613-2821-6"}],"event":{"name":"2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)","start":{"date-parts":[[2022,4,6]]},"location":"Prague, Czech Republic","end":{"date-parts":[[2022,4,8]]}},"container-title":["2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9770102\/9770107\/09770145.pdf?arnumber=9770145","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,20]],"date-time":"2022-06-20T17:32:00Z","timestamp":1655746320000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9770145\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,4,6]]},"references-count":35,"URL":"https:\/\/doi.org\/10.1109\/ddecs54261.2022.9770145","relation":{},"subject":[],"published":{"date-parts":[[2022,4,6]]}}}