{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,7]],"date-time":"2026-01-07T07:52:36Z","timestamp":1767772356628},"reference-count":10,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,5,3]],"date-time":"2023-05-03T00:00:00Z","timestamp":1683072000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,5,3]],"date-time":"2023-05-03T00:00:00Z","timestamp":1683072000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,5,3]]},"DOI":"10.1109\/ddecs57882.2023.10139343","type":"proceedings-article","created":{"date-parts":[[2023,6,2]],"date-time":"2023-06-02T19:34:34Z","timestamp":1685734474000},"source":"Crossref","is-referenced-by-count":4,"title":["Characterization of Interconnect Fault Effects in SRAM-based FPGAs"],"prefix":"10.1109","author":[{"given":"Christian","family":"Fibich","sequence":"first","affiliation":[{"name":"UAS Technikum Wien,Dept. of Electronic Engineering,Vienna,Austria"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Martin","family":"Horauer","sequence":"additional","affiliation":[{"name":"UAS Technikum Wien,Dept. of Electronic Engineering,Vienna,Austria"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Roman","family":"Obermaisser","sequence":"additional","affiliation":[{"name":"University of Siegen,Chair for Embedded Systems,Siegen,Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref8","article-title":"Root Cause Analysis and Classification of Single Point Failures in Designs Applying Triple Modular Redundancy in SRAM FPGAs","author":"swift","year":"2020","journal-title":"Brigham Young University M Sc Thesis"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.23919\/DATE51398.2021.9474161"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2018.00031"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2019.2898894"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/RSP.2018.8632000"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-013-5387-7"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-7595-9_2"},{"key":"ref10","article-title":"Interconnect multiplexers and methods of reducing contention currents in an interconnect multiplexer","author":"santurkar","year":"2016","journal-title":"US Patent 9 509 307 B1"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.3390\/electronics9010175"},{"key":"ref1","year":"2012","journal-title":"Soft Error Mitigation Using Prioritized Essential Bits XAPP538 (V1 0)"}],"event":{"name":"2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)","location":"Tallinn, Estonia","start":{"date-parts":[[2023,5,3]]},"end":{"date-parts":[[2023,5,5]]}},"container-title":["2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10139314\/10138940\/10139343.pdf?arnumber=10139343","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,6,19]],"date-time":"2023-06-19T17:49:14Z","timestamp":1687196954000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10139343\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,5,3]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/ddecs57882.2023.10139343","relation":{},"subject":[],"published":{"date-parts":[[2023,5,3]]}}}