{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T21:30:20Z","timestamp":1725658220423},"reference-count":17,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,5,3]],"date-time":"2023-05-03T00:00:00Z","timestamp":1683072000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,5,3]],"date-time":"2023-05-03T00:00:00Z","timestamp":1683072000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,5,3]]},"DOI":"10.1109\/ddecs57882.2023.10139428","type":"proceedings-article","created":{"date-parts":[[2023,6,2]],"date-time":"2023-06-02T19:34:34Z","timestamp":1685734474000},"page":"61-64","source":"Crossref","is-referenced-by-count":0,"title":["Supporting analog design for reliability by efficient provision of reliability information to designers"],"prefix":"10.1109","author":[{"given":"Fabio A.","family":"Velarde Gonzalez","sequence":"first","affiliation":[{"name":"Fraunhofer Institute for Integrated Circuits IIS,Division Engineering of Adaptive Systems EAS,Dresden,Germany"}]},{"given":"Lukas","family":"Hahne","sequence":"additional","affiliation":[{"name":"Fraunhofer Institute for Integrated Circuits IIS,Division Engineering of Adaptive Systems EAS,Dresden,Germany"}]},{"given":"Katrin","family":"Ortstein","sequence":"additional","affiliation":[{"name":"Fraunhofer Institute for Integrated Circuits IIS,Division Engineering of Adaptive Systems EAS,Dresden,Germany"}]},{"given":"Andr\u00e9","family":"Lange","sequence":"additional","affiliation":[{"name":"Fraunhofer Institute for Integrated Circuits IIS,Division Engineering of Adaptive Systems EAS,Dresden,Germany"}]},{"given":"Sonja","family":"Crocoll","sequence":"additional","affiliation":[{"name":"X-FAB Dresden GmbH &amp; Co. KG,Dresden,Germany"}]}],"member":"263","reference":[{"year":"0","key":"ref13"},{"year":"0","key":"ref12"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2011.2153854"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/IIRW53245.2021.9635606"},{"year":"0","key":"ref11"},{"year":"0","key":"ref10"},{"key":"ref2","article-title":"Analog Reliability Analysis for Mission-Critical Applications","author":"schaldenbrand","year":"2019","journal-title":"White paper Cadence Design Systems Inc"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4614-6163-0"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS48227.2022.9764418"},{"year":"0","key":"ref16"},{"journal-title":"JEDEC Standard JESD89","article-title":"A Procedure for Measuring P-Channel MOSFET Negative Bias Temperature Instabilities","year":"2004","key":"ref8"},{"journal-title":"JEDEC Standard JESD61","article-title":"A Procedure for Measuring P-Channel MOSFET Hot-Carrier-Induced Degradation Under DC Stress","year":"2004","key":"ref7"},{"article-title":"The 2020 Wilson Research Group Functional Verification Study &#x2013; Part 8 IC\/ASIC Resource Trends","year":"2021","author":"foster","key":"ref9"},{"key":"ref4","article-title":"MOS Device Aging Analysis with HSPICE and CustomSim","author":"tudor","year":"2011","journal-title":"Synopsys Inc White Paper"},{"key":"ref3","article-title":"Addressing IC Reliability Issues Using Eldo","author":"selim","year":"2016","journal-title":"Mentor Graphics Corporation white paper"},{"journal-title":"JEDEC Standard JESD22-A120","article-title":"Procedure for Measuring N-Channel MOSFET Hot-Carrier-Induced Degradation Under DC Stress","year":"2001","key":"ref6"},{"year":"0","key":"ref5"}],"event":{"name":"2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)","start":{"date-parts":[[2023,5,3]]},"location":"Tallinn, Estonia","end":{"date-parts":[[2023,5,5]]}},"container-title":["2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10139314\/10138940\/10139428.pdf?arnumber=10139428","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,6,19]],"date-time":"2023-06-19T17:49:14Z","timestamp":1687196954000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10139428\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,5,3]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/ddecs57882.2023.10139428","relation":{},"subject":[],"published":{"date-parts":[[2023,5,3]]}}}