{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T16:03:20Z","timestamp":1780675400995,"version":"3.54.1"},"reference-count":12,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,4,3]],"date-time":"2024-04-03T00:00:00Z","timestamp":1712102400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,4,3]],"date-time":"2024-04-03T00:00:00Z","timestamp":1712102400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,4,3]]},"DOI":"10.1109\/ddecs60919.2024.10508913","type":"proceedings-article","created":{"date-parts":[[2024,4,30]],"date-time":"2024-04-30T17:35:37Z","timestamp":1714498537000},"page":"73-78","source":"Crossref","is-referenced-by-count":1,"title":["Improving Virtual Prototype Driven Hardware Optimization by Merging Instruction Sequences"],"prefix":"10.1109","author":[{"given":"Jan","family":"Zielasko","sequence":"first","affiliation":[{"name":"Institute of Computer Science, University of Bremen,Bremen,Germany,28359"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Rune","family":"Krauss","sequence":"additional","affiliation":[{"name":"Institute of Computer Science, University of Bremen,Bremen,Germany,28359"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Marcel","family":"Merten","sequence":"additional","affiliation":[{"name":"Institute of Computer Science, University of Bremen,Bremen,Germany,28359"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Rolf","family":"Drechsler","sequence":"additional","affiliation":[{"name":"Institute of Computer Science, University of Bremen,Bremen,Germany,28359"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TLA.2020.9085271"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3140659.3080247"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/978-0-387-73543-6_16"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.14445\/23488379\/ijeee-v6i7p101"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/eeei.2010.5662163"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/FDL59689.2023.10272131"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS54261.2022.9770108"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2013.7478332"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3603781.3603942"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-54828-5"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2020.101756"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/b137175"}],"event":{"name":"2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS)","location":"Kielce, Poland","start":{"date-parts":[[2024,4,3]]},"end":{"date-parts":[[2024,4,5]]}},"container-title":["2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10508803\/10508898\/10508913.pdf?arnumber=10508913","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,5,3]],"date-time":"2024-05-03T18:26:55Z","timestamp":1714760815000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10508913\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,4,3]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/ddecs60919.2024.10508913","relation":{},"subject":[],"published":{"date-parts":[[2024,4,3]]}}}