{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,29]],"date-time":"2025-10-29T03:48:38Z","timestamp":1761709718147,"version":"3.28.0"},"reference-count":21,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,5,1]],"date-time":"2020-05-01T00:00:00Z","timestamp":1588291200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,5,1]],"date-time":"2020-05-01T00:00:00Z","timestamp":1588291200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,5,1]],"date-time":"2020-05-01T00:00:00Z","timestamp":1588291200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,5]]},"DOI":"10.1109\/dessert50317.2020.9125070","type":"proceedings-article","created":{"date-parts":[[2020,6,25]],"date-time":"2020-06-25T20:46:07Z","timestamp":1593117967000},"page":"52-57","source":"Crossref","is-referenced-by-count":2,"title":["Reversible Majority Voter Based on Fredkin Gates"],"prefix":"10.1109","author":[{"given":"Sergey F.","family":"Tyurin","sequence":"first","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/s40031-019-00413-z"},{"article-title":"Triple Module Redundancy Design Techniques for Virtex FPGAs","year":"0","author":"carmichael","key":"ref11"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1016\/j.tcs.2004.12.026"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/PACRIM.2017.8121882"},{"key":"ref14","article-title":"Adder Designs using Reversible Logic Gates","author":"lala","year":"0","journal-title":"WSEAS Transactions on Circuits and Systems"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICECDS.2017.8389908"},{"key":"ref16","first-page":"654","article-title":"Improving of a Circuit Checkability and Trustworthiness of Data Processing Results in LUT-based FPGA Components of Safety-Related Systems","volume":"1844","author":"drozd","year":"2017","journal-title":"CEUR Workshop Proceedings"},{"key":"ref17","first-page":"322","article-title":"Use of Natural LUT Redundancy to Improve Trustworthiness of FPGA Design","volume":"1614","author":"drozd","year":"2016","journal-title":"CEUR Workshop Proceedings"},{"key":"ref18","doi-asserted-by":"crossref","first-page":"23","DOI":"10.15588\/1607-3274-2019-2-3","article-title":"Investigation of a Hybrid Redundancy in the Fault-Tolerant Systems","volume":"2","author":"tyurin","year":"2019","journal-title":"Radio Electronics Computer Science Control"},{"key":"ref19","doi-asserted-by":"crossref","first-page":"258","DOI":"10.47839\/ijc.18.3.1518","article-title":"A Quad CMOS gates checking method","volume":"117","author":"tyurin","year":"2019","journal-title":"International Journal of Computing"},{"journal-title":"Reversible computing","year":"0","key":"ref4"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/978-4-431-56606-9"},{"article-title":"DFT methodologies for testing k-CNOT, Fredkin and Peres based reversible circuits","year":"0","author":"ravichander","key":"ref6"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1080\/00207217.2019.1608587"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/978-981-13-8821-7_9"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-019-05811-1"},{"key":"ref2","first-page":"2772","article-title":"Design of Reversible Sequential Circuits using FredkinFeynman Gate in QCA","volume":"4","author":"manga","year":"2015","journal-title":"IJSETR International Journal of Science Engineering and Technology Research"},{"article-title":"Design and Testing of Reversible Logic. Book","year":"2020","author":"kumar","key":"ref1"},{"article-title":"A New Perspective in Designing an Optimized Fault Tolerant Reversible Multiplier","year":"0","author":"shahmi","key":"ref9"},{"journal-title":"CAD MicroWind","year":"0","key":"ref20"},{"article-title":"BSIM4v4.8.0 MOSFET Model -User&#x2019;s Manual 2013","year":"0","author":"paydavosi","key":"ref21"}],"event":{"name":"2020 IEEE 11th International Conference on Dependable Systems, Services and Technologies (DESSERT)","start":{"date-parts":[[2020,5,14]]},"location":"Kyiv, Ukraine","end":{"date-parts":[[2020,5,18]]}},"container-title":["2020 IEEE 11th International Conference on Dependable Systems, Services and Technologies (DESSERT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9122248\/9124995\/09125070.pdf?arnumber=9125070","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,27]],"date-time":"2022-06-27T15:55:18Z","timestamp":1656345318000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9125070\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,5]]},"references-count":21,"URL":"https:\/\/doi.org\/10.1109\/dessert50317.2020.9125070","relation":{},"subject":[],"published":{"date-parts":[[2020,5]]}}}