{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T10:43:31Z","timestamp":1761561811629},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,10]]},"DOI":"10.1109\/dft.2013.6653596","type":"proceedings-article","created":{"date-parts":[[2013,11,11]],"date-time":"2013-11-11T14:58:04Z","timestamp":1384181884000},"page":"137-142","source":"Crossref","is-referenced-by-count":9,"title":["Synthesis of workload monitors for on-line stress prediction"],"prefix":"10.1109","author":[{"given":"Rafal","family":"Baranowski","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alejandro","family":"Cook","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael E.","family":"Imhof","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chang","family":"Liu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hans-Joachim","family":"Wunderlich","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI.2008.43"},{"year":"0","key":"16"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1985.1585936"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2007.910130"},{"key":"11","first-page":"29","article-title":"A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor","author":"mukherjee","year":"2009","journal-title":"Proc IEEE IACM IntI Symposium on Microarchitecture (MICRO-36)"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1978.1675075"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2009.5117765"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.917502"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2007.378339"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1993.580054"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1117\/12.462807"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2008.4700619"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5457131"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5457203"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1145\/1273440.1250726"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.838021"}],"event":{"name":"2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)","start":{"date-parts":[[2013,10,2]]},"location":"New York City, NY, USA","end":{"date-parts":[[2013,10,4]]}},"container-title":["2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6644330\/6653572\/06653596.pdf?arnumber=6653596","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,22]],"date-time":"2017-03-22T21:57:40Z","timestamp":1490219860000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6653596\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,10]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/dft.2013.6653596","relation":{},"subject":[],"published":{"date-parts":[[2013,10]]}}}