{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T15:42:49Z","timestamp":1725810169258},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,10]]},"DOI":"10.1109\/dft.2014.6962090","type":"proceedings-article","created":{"date-parts":[[2014,12,1]],"date-time":"2014-12-01T18:16:22Z","timestamp":1417457782000},"page":"299-304","source":"Crossref","is-referenced-by-count":20,"title":["On the in-field functional testing of decode units in pipelined RISC processors"],"prefix":"10.1109","author":[{"given":"P.","family":"Bernardi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"R.","family":"Cantoro","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"L.","family":"Ciganda","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"E.","family":"Sanchez","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M. Sonza","family":"Reorda","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S.","family":"De Luca","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"R.","family":"Meregalli","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Sansonetti","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"year":"0","key":"15"},{"journal-title":"EREF 2 0 A Programmer's Reference Manual for Freescale Power Architecture Processors","year":"0","key":"13"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2012.6233004"},{"journal-title":"ARM Cortex-A57 Mpcore processor revision R1p0 technical reference manual","year":"0","key":"11"},{"journal-title":"Specification of Core Test","year":"0","key":"12"},{"year":"0","key":"3"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.5"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1980.1675602"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCE-Berlin.2013.6697986"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2008.18"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763092"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.839486(410) 24"},{"year":"0","key":"4"},{"journal-title":"Computer Architecture A Quantitative Approach","year":"2011","author":"hennessy","key":"9"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2008.15"}],"event":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","start":{"date-parts":[[2014,10,1]]},"location":"Amsterdam, Netherlands","end":{"date-parts":[[2014,10,3]]}},"container-title":["2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6942523\/6962057\/06962090.pdf?arnumber=6962090","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T17:17:28Z","timestamp":1490289448000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6962090\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,10]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/dft.2014.6962090","relation":{},"subject":[],"published":{"date-parts":[[2014,10]]}}}