{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,13]],"date-time":"2026-03-13T14:56:58Z","timestamp":1773413818130,"version":"3.50.1"},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,10]]},"DOI":"10.1109\/dft.2017.8244434","type":"proceedings-article","created":{"date-parts":[[2018,1,9]],"date-time":"2018-01-09T21:19:51Z","timestamp":1515532791000},"page":"1-4","source":"Crossref","is-referenced-by-count":2,"title":["Preventing scan-based side-channel attacks through key masking"],"prefix":"10.1109","author":[{"given":"Satyadev","family":"Ahlawat","sequence":"first","affiliation":[]},{"given":"Darshit","family":"Vaghani","sequence":"additional","affiliation":[]},{"given":"Virendra","family":"Singh","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2089071"},{"key":"ref3","first-page":"119","article-title":"Secure scan techniques: A comparison","author":"h\u00e9ly","year":"0"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2138470"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2005.193787"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2007.89"},{"key":"ref8","first-page":"228","article-title":"A smart test controller for scan chains in secure circuits","author":"darolt","year":"0"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2016.10.011"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2014.2304492"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2017.7968241"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2010045"}],"event":{"name":"2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","location":"Cambridge","start":{"date-parts":[[2017,10,23]]},"end":{"date-parts":[[2017,10,25]]}},"container-title":["2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8227263\/8244422\/08244434.pdf?arnumber=8244434","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,2,5]],"date-time":"2018-02-05T22:35:34Z","timestamp":1517870134000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8244434\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,10]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/dft.2017.8244434","relation":{},"subject":[],"published":{"date-parts":[[2017,10]]}}}