{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T02:45:22Z","timestamp":1725504322529},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,10]]},"DOI":"10.1109\/dft.2017.8244438","type":"proceedings-article","created":{"date-parts":[[2018,1,9]],"date-time":"2018-01-09T21:19:51Z","timestamp":1515532791000},"page":"1-6","source":"Crossref","is-referenced-by-count":3,"title":["CAL: Exploring cost, accuracy, and latency in approximate and speculative adder design"],"prefix":"10.1109","author":[{"given":"Sina","family":"Boroumand","sequence":"first","affiliation":[]},{"given":"Hadi P.","family":"Afshar","sequence":"additional","affiliation":[]},{"given":"Philip","family":"Brisk","sequence":"additional","affiliation":[]},{"given":"Siamak","family":"Mohammadi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.3850\/9783981537079_0042"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2009.2027626"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2217962"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/NANO.2013.6720793"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763154"},{"key":"ref15","first-page":"95","article-title":"A low-power, high-performance approximate multiplier with configurable partial error recovery","author":"liu","year":"2014","journal-title":"Proc Design Automation & Test Europe Conf"},{"key":"ref16","first-page":"69","article-title":"An enhanced low-power high-speed adder for error-tolerant application","author":"zhu","year":"2009","journal-title":"Integrated Circuits ISIC'09 Proceedings of the 2009 12th International Symposium on"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2355217"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2208966"},{"key":"ref6","first-page":"1257","article-title":"High performance reliable variable latency carry select addition","author":"du","year":"2012","journal-title":"Design Automation & Test in Europe Conference & Exhibition (DATE)"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228509"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2013.6691108"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2013.6691096"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1403375.1403679"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2742060.2743760"},{"key":"ref9","first-page":"1449","article-title":"A new approximate adder with low relative error and correct sign calculation","author":"hu","year":"2015","journal-title":"Proceedings of the 2015 Design Automation & Test in Europe Conference & Exhibition EDA Consortium"}],"event":{"name":"2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","start":{"date-parts":[[2017,10,23]]},"location":"Cambridge","end":{"date-parts":[[2017,10,25]]}},"container-title":["2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8227263\/8244422\/08244438.pdf?arnumber=8244438","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,2,20]],"date-time":"2018-02-20T00:17:15Z","timestamp":1519085835000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8244438\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,10]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/dft.2017.8244438","relation":{},"subject":[],"published":{"date-parts":[[2017,10]]}}}