{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,3]],"date-time":"2024-09-03T20:59:02Z","timestamp":1725397142623},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,10]]},"DOI":"10.1109\/dft.2017.8244451","type":"proceedings-article","created":{"date-parts":[[2018,1,9]],"date-time":"2018-01-09T21:19:51Z","timestamp":1515532791000},"page":"1-6","source":"Crossref","is-referenced-by-count":0,"title":["Early estimation of aging in the design flow of integrated circuits through a programmable hardware module"],"prefix":"10.1109","author":[{"given":"Chiara","family":"Sandionigi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mauricio","family":"Altieri","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Olivier","family":"Heron","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2897980"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2015.7112784"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2014.6860673"},{"article-title":"Programmable test chip, system and method for characterization of integrated circuit fabrication processes","year":"2012","author":"mikkola","key":"ref6"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2009.5355742"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898082"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2013.2296118"},{"journal-title":"JEDEC","year":"0","key":"ref8"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2016.7604671"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.3850\/9783981537079_0091"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2011.6122367"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2012.6241830"}],"event":{"name":"2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","start":{"date-parts":[[2017,10,23]]},"location":"Cambridge","end":{"date-parts":[[2017,10,25]]}},"container-title":["2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8227263\/8244422\/08244451.pdf?arnumber=8244451","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,2,5]],"date-time":"2018-02-05T22:35:33Z","timestamp":1517870133000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8244451\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,10]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/dft.2017.8244451","relation":{},"subject":[],"published":{"date-parts":[[2017,10]]}}}