{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T10:48:21Z","timestamp":1761648501921,"version":"3.28.0"},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,10]]},"DOI":"10.1109\/dft.2017.8244455","type":"proceedings-article","created":{"date-parts":[[2018,1,9]],"date-time":"2018-01-09T16:19:51Z","timestamp":1515514791000},"page":"1-4","source":"Crossref","is-referenced-by-count":3,"title":["Scheduling voter checks to detect configuration memory errors in FPGA-based TMR systems"],"prefix":"10.1109","author":[{"given":"Nguyen T. H.","family":"Nguyen","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ediz","family":"Cetin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Oliver","family":"Diessel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2016.7929525"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2012.09.006"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1016\/j.ejor.2009.05.024"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2017.17"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2012.2231881"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2009.2033381"},{"journal-title":"Fault-Tolerant Systems","year":"2007","author":"koren","key":"ref8"},{"key":"ref7","article-title":"Soft error mitigation using prioritized essential bits","volume":"v1 0","author":"le","year":"2012","journal-title":"Xilinx XAPP 538"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2016.30"},{"key":"ref9","article-title":"Scheduling Considerations for Voter Checking in FPGA-based TMR Systems","author":"nguyen","year":"2017","journal-title":"UNSW CSE"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2010.281"}],"event":{"name":"2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","start":{"date-parts":[[2017,10,23]]},"location":"Cambridge","end":{"date-parts":[[2017,10,25]]}},"container-title":["2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8227263\/8244422\/08244455.pdf?arnumber=8244455","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,2,5]],"date-time":"2018-02-05T17:35:31Z","timestamp":1517852131000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8244455\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,10]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/dft.2017.8244455","relation":{},"subject":[],"published":{"date-parts":[[2017,10]]}}}