{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T12:24:09Z","timestamp":1725625449464},"reference-count":12,"publisher":"IEEE","license":[{"start":{"date-parts":[[2018,10,1]],"date-time":"2018-10-01T00:00:00Z","timestamp":1538352000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2018,10,1]],"date-time":"2018-10-01T00:00:00Z","timestamp":1538352000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,10]]},"DOI":"10.1109\/dft.2018.8602934","type":"proceedings-article","created":{"date-parts":[[2019,1,9]],"date-time":"2019-01-09T01:46:18Z","timestamp":1546998378000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["MATS**: An On-Line Testing Approach for Reconfigurable Embedded Memories"],"prefix":"10.1109","author":[{"given":"Ludovica","family":"Bozzoli","sequence":"first","affiliation":[{"name":"Informatica Politecnico di Torino, Dipartimento di Automatica e, Torino, Italy"}]},{"given":"Luca","family":"Sterpone","sequence":"additional","affiliation":[{"name":"Informatica Politecnico di Torino, Dipartimento di Automatica e, Torino, Italy"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/SSST.2011.5753810"},{"key":"ref3","article-title":"COMET: a configuration memory tool to analyze, visualize and manipulate FPGAs bitstream","author":"bozzoli","year":"2018","journal-title":"ARCS 2018 31th International Conference on Architecture of Computing Systems"},{"key":"ref10","first-page":"319","article-title":"Fast partial reconfiguration on SRAM-based FPGAs: A frame-driven routing approach","author":"sterpone","year":"2018","journal-title":"International Symposium on Applied Reconfigurable Computing"},{"journal-title":"7 Series FPGAs Memory Resources User Guide UG473 v1 12","year":"2016","key":"ref6"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1268908"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TR.2003.821927"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2014.6873681"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041813"},{"journal-title":"Xilinx LogiCORE IP ECC v2 0 Product Guide for Vivado Design Suite PG092","year":"2017","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2013.80"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISICIR.2014.7029438"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2017.16"}],"event":{"name":"2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","start":{"date-parts":[[2018,10,8]]},"location":"Chicago, IL, USA","end":{"date-parts":[[2018,10,10]]}},"container-title":["2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8586781\/8602813\/08602934.pdf?arnumber=8602934","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,1,24]],"date-time":"2023-01-24T19:15:46Z","timestamp":1674587746000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8602934\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,10]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/dft.2018.8602934","relation":{},"subject":[],"published":{"date-parts":[[2018,10]]}}}