{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,3]],"date-time":"2024-09-03T20:46:37Z","timestamp":1725396397765},"reference-count":25,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,10]]},"DOI":"10.1109\/dft.2018.8602967","type":"proceedings-article","created":{"date-parts":[[2019,1,9]],"date-time":"2019-01-09T01:46:18Z","timestamp":1546998378000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["Postprocessing Procedure for Reducing the Faulty Switching Activity of a Low-Power Test Set"],"prefix":"10.1109","author":[{"given":"Irith","family":"Pomeranz","sequence":"first","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"1019","article-title":"Low-Capture-Power Test Generation for Scan-Based Testing","author":"wen","year":"2005","journal-title":"Proc Intl Test Conf"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2007.364648"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"1172","DOI":"10.1145\/1403375.1403661","article-title":"Layout-aware, IR-drop Tolerant Transition Fault Pattern Generation","author":"lee","year":"2008","journal-title":"Proc Design Autom and Test in Europe Conf"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2008.47"},{"journal-title":"Power-Aware Testing and Test Strategies for Low Power Devices","year":"2009","author":"girard","key":"ref14"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2030353"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2010.5469580"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2010.5419834"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2013.40"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2282281"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.2000.843824"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/43.736572"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2001.966687"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2000.893666"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2003.1219118"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2002.1011128"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2008.4700586"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996706"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1271098"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2275037"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2015.7138773"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2311170"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2015.10"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2332465"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2016.12"}],"event":{"name":"2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","start":{"date-parts":[[2018,10,8]]},"location":"Chicago, IL","end":{"date-parts":[[2018,10,10]]}},"container-title":["2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8586781\/8602813\/08602967.pdf?arnumber=8602967","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,26]],"date-time":"2022-01-26T00:42:07Z","timestamp":1643157727000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8602967\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,10]]},"references-count":25,"URL":"https:\/\/doi.org\/10.1109\/dft.2018.8602967","relation":{},"subject":[],"published":{"date-parts":[[2018,10]]}}}