{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,21]],"date-time":"2026-01-21T20:26:41Z","timestamp":1769027201555,"version":"3.49.0"},"reference-count":20,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,10]]},"DOI":"10.1109\/dft.2018.8602981","type":"proceedings-article","created":{"date-parts":[[2019,1,9]],"date-time":"2019-01-09T01:46:18Z","timestamp":1546998378000},"page":"1-6","source":"Crossref","is-referenced-by-count":9,"title":["45nm Bit-Interleaving Differential 10T Low Leakage FinFET Based SRAM with Column-Wise Write Access Control"],"prefix":"10.1109","author":[{"given":"Vishal","family":"Gupta","sequence":"first","affiliation":[]},{"given":"Saurabh","family":"Khandelwal","sequence":"additional","affiliation":[]},{"given":"Jimson","family":"Mathew","sequence":"additional","affiliation":[]},{"given":"Marco","family":"Ottavi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2012.05.014"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1077603.1077607"},{"key":"ref12","first-page":"520","article-title":"PSP based scalable compact FinFET model","volume":"3","author":"smit","year":"2007","journal-title":"Proc Workshop Compact Model NSTI-Nanotech"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ICNETS2.2017.8067965"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/.2005.1469239"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.914328"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2010.2057230"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.891726"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2011972"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2106523"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/NANOARCH.2015.7180588"},{"key":"ref3","article-title":"Low Power Design Essentials","author":"rabaey","year":"2009","journal-title":"Springer-Verlag US"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2013.2291064"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1166\/jctn.2012.2139"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2014.2359572"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1080\/03772063.2017.1393351"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2010.2046988"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MCAS.2011.942068"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2003.1269336"},{"key":"ref20","doi-asserted-by":"crossref","first-page":"810","DOI":"10.1166\/jno.2015.1843","article-title":"Process variability aware low leakage reliable nano scale double-gate-FinFET SRAM cell design technique","volume":"10","author":"gupta","year":"2015","journal-title":"Journal of Nanoelectronics and Optoelectronics"}],"event":{"name":"2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","location":"Chicago, IL","start":{"date-parts":[[2018,10,8]]},"end":{"date-parts":[[2018,10,10]]}},"container-title":["2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8586781\/8602813\/08602981.pdf?arnumber=8602981","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,26]],"date-time":"2022-01-26T01:17:00Z","timestamp":1643159820000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8602981\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,10]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/dft.2018.8602981","relation":{},"subject":[],"published":{"date-parts":[[2018,10]]}}}