{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T15:09:29Z","timestamp":1730214569370,"version":"3.28.0"},"reference-count":24,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,10]]},"DOI":"10.1109\/dft.2018.8602985","type":"proceedings-article","created":{"date-parts":[[2019,1,9]],"date-time":"2019-01-09T01:46:18Z","timestamp":1546998378000},"page":"1-6","source":"Crossref","is-referenced-by-count":0,"title":["Multiple Fault Detection in Nano Programmable Logic Arrays"],"prefix":"10.1109","author":[{"given":"Pilin","family":"Junsangsri","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Fabrizio","family":"Lombardi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"462","article-title":"CAEN-BIST: Testing the NanoFabric","author":"brown","year":"2005","journal-title":"Proc IEEE ITC"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1981.1675712"},{"key":"ref12","first-page":"131","article-title":"FITPLA: A Programmable Logic Array for Function Independent Testing","author":"hong","year":"1980","journal-title":"Proc 1980 Int Symp Fault Tolerant Computing"},{"key":"ref13","first-page":"252","article-title":"A Fault Model for PLA","author":"lighthart","year":"1989","journal-title":"Proc of the 1989 Euro Test Conf"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/5.752520"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/43.293950"},{"key":"ref16","first-page":"146","article-title":"A New Method for Testing EEPLA's","author":"munshi","year":"1998","journal-title":"Proc IEEE Int Symp on Defect and Fault Tolerance in VLSI Systems"},{"key":"ref17","first-page":"204","article-title":"On the Diagnosis of Programmable Interconnects: Theory and Applications","author":"lombardi","year":"1996","journal-title":"Proc IEEE VLSI Test Symposium"},{"key":"ref18","first-page":"126","article-title":"Testing and Diagnosis of Interconnects using Boundary-scan","author":"hassan","year":"1985","journal-title":"Proc IEEE International Test Conference"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1974.223950"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2001.937446"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1063\/1.1823026"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2003.820804"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1021\/ar000178q"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1038\/nmat1123"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1084748.1084750"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2003.808508"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"112","DOI":"10.1126\/science.1081940","article-title":"Ultra High-density Nanowire Lattices and Circuits","volume":"300","author":"melosh","year":"2003","journal-title":"Science"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"2418","DOI":"10.1126\/science.1070821","article-title":"Self-Assembly at All Levels","volume":"295","author":"whitesides","year":"2002","journal-title":"Science"},{"key":"ref20","first-page":"1037","article-title":"Detection of Bridging Faults in Logic Resources of Configurable FPGAs Using IDDQ","author":"zhao","year":"1998","journal-title":"Proc IEEE Int Test Conf"},{"key":"ref22","first-page":"100","article-title":"Diagnosing Programmable Interconnect Systems for FPGAs","author":"lombardi","year":"1996","journal-title":"Proc ACM International Symposium on FPGAs"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.1995.476956"},{"key":"ref24","first-page":"52","article-title":"Interconnect Testing with Boundary Scan","author":"wagner","year":"1987","journal-title":"Proc IEEE International Test Conference"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1271109"}],"event":{"name":"2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","start":{"date-parts":[[2018,10,8]]},"location":"Chicago, IL","end":{"date-parts":[[2018,10,10]]}},"container-title":["2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8586781\/8602813\/08602985.pdf?arnumber=8602985","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,26]],"date-time":"2022-01-26T01:01:10Z","timestamp":1643158870000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8602985\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,10]]},"references-count":24,"URL":"https:\/\/doi.org\/10.1109\/dft.2018.8602985","relation":{},"subject":[],"published":{"date-parts":[[2018,10]]}}}