{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T04:36:35Z","timestamp":1729658195804,"version":"3.28.0"},"reference-count":20,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,10]]},"DOI":"10.1109\/dft.2019.8875328","type":"proceedings-article","created":{"date-parts":[[2019,10,22]],"date-time":"2019-10-22T00:19:21Z","timestamp":1571703561000},"page":"1-6","source":"Crossref","is-referenced-by-count":0,"title":["Predicting Single Event Effects in DRAM"],"prefix":"10.1109","author":[{"given":"Donald","family":"Kline","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Stephen","family":"Longofono","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rami","family":"Melhem","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alex K.","family":"Jones","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"crossref","first-page":"461","DOI":"10.1145\/2024723.2000118","article-title":"Energy-efficient cache design using variable-strength error-correcting codes","volume":"39","author":"alameldeen","year":"2011","journal-title":"SIGARCH Comput Archit News"},{"key":"ref11","article-title":"Chipkill correct memory architecture","author":"locklear","year":"2000","journal-title":"Dell Enterprise Systems Group Technology brief"},{"key":"ref12","first-page":"1","article-title":"A white paper on the benefits of chipkill-correct ecc for pc server main memory","volume":"11","author":"dell","year":"1997","journal-title":"IBM Microelectronics Division"},{"key":"ref13","article-title":"Chipkill memory","author":"shutler","year":"2005","journal-title":"IBM Eserver"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1816038.1815980"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056058"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2012.6378619"},{"key":"ref17","article-title":"Archshield: Architectural framework for assisting dram scaling by tolerating high error rates","author":"nair","year":"2013","journal-title":"ISCA"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/IGCC.2017.8323584"},{"journal-title":"Memtest86+","article-title":"Official site of the x86 memory testing tool","year":"2019","key":"ref19"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2015.2392851"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"2534","DOI":"10.1109\/23.903804","article-title":"Analysis of radiation effects on individual dram cells","volume":"47","author":"scheick","year":"2000","journal-title":"IEEE Transactions on Nuclear Science"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"147","DOI":"10.1002\/j.1538-7305.1950.tb00463.x","article-title":"Error detecting and error correcting codes","volume":"29","author":"hamming","year":"1950","journal-title":"Bell Labs Technical Journal"},{"key":"ref5","first-page":"126","author":"ladbury","year":"0","journal-title":"Radiation performance of 1 gbit ddr sdrams fabricated in the 90 nm cmos technology node"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"89","DOI":"10.1145\/1669112.1669126","article-title":"Improving cache lifetime reliability at ultra-low voltages","author":"chishti","year":"2009","journal-title":"MICRO 42"},{"key":"ref7","first-page":"197","article-title":"Multi-bit error tolerant caches using two-dimensional error coding","author":"kim","year":"2007","journal-title":"MICRO 40"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2678373.2665726"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2016.30"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"83","DOI":"10.1145\/1816038.1815973","article-title":"Reducing cache power with low-cost, multi-bit error-correcting codes","volume":"38","author":"wilkerson","year":"2010","journal-title":"SIGARCH Comput Archit News"},{"journal-title":"Micron T Tech Rep","article-title":"3d xpoint technology","year":"2015","key":"ref20"}],"event":{"name":"2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","start":{"date-parts":[[2019,10,2]]},"location":"Noordwijk, Netherlands","end":{"date-parts":[[2019,10,4]]}},"container-title":["2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8863044\/8875268\/08875328.pdf?arnumber=8875328","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,9,21]],"date-time":"2023-09-21T22:49:10Z","timestamp":1695336550000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8875328\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,10]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/dft.2019.8875328","relation":{},"subject":[],"published":{"date-parts":[[2019,10]]}}}