{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,11]],"date-time":"2025-11-11T22:23:43Z","timestamp":1762899823144,"version":"3.28.0"},"reference-count":22,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,10]]},"DOI":"10.1109\/dft.2019.8875396","type":"proceedings-article","created":{"date-parts":[[2019,10,22]],"date-time":"2019-10-22T00:19:21Z","timestamp":1571703561000},"page":"1-4","source":"Crossref","is-referenced-by-count":3,"title":["Protecting Large Word Size Memories against MCUs with 3-bit Burst Error Correction"],"prefix":"10.1109","author":[{"given":"Jiaqiang","family":"Li","sequence":"first","affiliation":[]},{"given":"Pedro","family":"Reviriego","sequence":"additional","affiliation":[]},{"given":"Liyi","family":"Xiao","sequence":"additional","affiliation":[]},{"given":"Alexander","family":"Klockmann","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2007.40"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2012.2232671"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/VLSISoC.2011.6081647"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2319291"},{"key":"ref14","first-page":"150157","article-title":"A Class of Systematic Codes for Non-Independent Errors","volume":"5","author":"abramson","year":"1959","journal-title":"IRE Transactions on Information Theory"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2357476"},{"key":"ref16","first-page":"219","author":"abhishek","year":"2018","journal-title":"Low Complexity Burst Error Correcting Codes to Correct MBUs in SRAMs"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2011.2176513"},{"journal-title":"Systematic Design of a New 3-Bit-Burst-Error Correction Code with Minimal Number of Check Bits","year":"2017","author":"klockmann","key":"ref18"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2017.8046167"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1002\/j.1538-7305.1950.tb00463.x"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1147\/rd.282.0124"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2010.2047907"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"395","DOI":"10.1147\/rd.144.0395","article-title":"A class of optimal minimum odd-weight-column SEC-DED codes","volume":"14","author":"hsiao","year":"1970","journal-title":"IBM J Res Develop"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2009.2015312"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/55.843160"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2008.2007646"},{"journal-title":"Dependability in Electronic Systems Mitigation of Hardware Failures Soft Errors and Electro-Magnetic Disturbances","year":"2010","author":"kanekawa","key":"ref1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2010.2042818"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2766361"},{"key":"ref22","article-title":"A Class of multiple-error-correcting binary codes for nonindependent errors","author":"fire","year":"1959","journal-title":"Sylvania Report RSL-E-2"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.1971.1054581"}],"event":{"name":"2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","start":{"date-parts":[[2019,10,2]]},"location":"Noordwijk, Netherlands","end":{"date-parts":[[2019,10,4]]}},"container-title":["2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8863044\/8875268\/08875396.pdf?arnumber=8875396","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,19]],"date-time":"2022-07-19T20:25:26Z","timestamp":1658262326000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8875396\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,10]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/dft.2019.8875396","relation":{},"subject":[],"published":{"date-parts":[[2019,10]]}}}