{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,26]],"date-time":"2025-09-26T13:12:43Z","timestamp":1758892363655},"reference-count":12,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,10]]},"DOI":"10.1109\/dft.2019.8875431","type":"proceedings-article","created":{"date-parts":[[2019,10,22]],"date-time":"2019-10-22T00:19:21Z","timestamp":1571703561000},"source":"Crossref","is-referenced-by-count":13,"title":["Scatter Scrubbing: A Method to Reduce SEU Repair Time in FPGA Configuration Memory"],"prefix":"10.1109","author":[{"given":"Mahsa","family":"Mousavi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hamid Reza","family":"Pourshaghaghi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Henk","family":"Corporaal","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Akash","family":"Kumar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2009.5272543"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645533"},{"key":"ref10","year":"2018","journal-title":"7 Series FPGA Configuration User Guide"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISIE.2010.5637493"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1002\/nav.3800030106"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2095435"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2018.00050"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2014.6927448"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2036362"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/RSP.2015.7416555"},{"key":"ref9","year":"2018","journal-title":"Soft Error Mitigation Controller v4 1 Product Guide"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2010.281"}],"event":{"name":"2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","location":"Noordwijk, Netherlands","start":{"date-parts":[[2019,10,2]]},"end":{"date-parts":[[2019,10,4]]}},"container-title":["2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8863044\/8875268\/08875431.pdf?arnumber=8875431","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,19]],"date-time":"2022-07-19T20:25:27Z","timestamp":1658262327000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8875431\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,10]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/dft.2019.8875431","relation":{},"subject":[],"published":{"date-parts":[[2019,10]]}}}