{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,23]],"date-time":"2025-08-23T05:21:44Z","timestamp":1755926504404,"version":"3.28.0"},"reference-count":20,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,10,19]],"date-time":"2020-10-19T00:00:00Z","timestamp":1603065600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,10,19]],"date-time":"2020-10-19T00:00:00Z","timestamp":1603065600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,10,19]],"date-time":"2020-10-19T00:00:00Z","timestamp":1603065600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,10,19]]},"DOI":"10.1109\/dft50435.2020.9250871","type":"proceedings-article","created":{"date-parts":[[2020,11,11]],"date-time":"2020-11-11T22:04:48Z","timestamp":1605132288000},"page":"1-6","source":"Crossref","is-referenced-by-count":21,"title":["Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment"],"prefix":"10.1109","author":[{"given":"Marcello","family":"Barbirotta","sequence":"first","affiliation":[]},{"given":"Antonio","family":"Mastrandrea","sequence":"additional","affiliation":[]},{"given":"Francesco","family":"Menichelli","sequence":"additional","affiliation":[]},{"given":"Francesco","family":"Vigli","sequence":"additional","affiliation":[]},{"given":"Luigi","family":"Blasi","sequence":"additional","affiliation":[]},{"given":"Abdallah","family":"Cheikh","sequence":"additional","affiliation":[]},{"given":"Stefano","family":"Sordillo","sequence":"additional","affiliation":[]},{"given":"Fabio","family":"Di Gennaro","sequence":"additional","affiliation":[]},{"given":"Mauro","family":"Olivieri","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1109\/LASCAS.2018.8399945"},{"key":"ref11","first-page":"96","article-title":"Hight Speed Fault Injection Tool Implemented With Verilog HDL on FPGA for Testing Fault Tolerance Designs","volume":"3","author":"gopinath reddy","year":"2013","journal-title":"Int Journal of Engineering Research and Applications"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1109\/OLT.2003.1214387"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1109\/OLT.2004.1319692"},{"doi-asserted-by":"publisher","key":"ref14","DOI":"10.1007\/978-3-319-93082-4_12"},{"doi-asserted-by":"publisher","key":"ref15","DOI":"10.1109\/NGCAS.2017.61"},{"key":"ref16","first-page":"505","article-title":"Efficient mathematic accelerator design coupled with an IMT RISC-V microprocessor","volume":"627","author":"cheikh","year":"2020","journal-title":"Applepies 2019 Lecture Notes in Electrical Engineering"},{"doi-asserted-by":"publisher","key":"ref17","DOI":"10.1109\/EEEI.2014.7005803"},{"doi-asserted-by":"publisher","key":"ref18","DOI":"10.1109\/ICEOE.2011.6013043"},{"key":"ref19","article-title":"Easier UVM for Functional Verification by Mainstream Users","author":"john aynsley","year":"2011","journal-title":"DVCon 2011"},{"key":"ref4","article-title":"An FPGA-based RISC-V Computer Architecture Orbital Laboratory on a PocketCube Satellite","author":"blasi","year":"2019","journal-title":"Proc of 5th IAA Conference on University Satellite Missions and CubeSat Workshop"},{"key":"ref3","first-page":"581","article-title":"A space-rated soft IP-core compatible with the PIC&#x00AE; hardware architecture and instruction set","volume":"163","author":"blasi","year":"2018","journal-title":"Adv Astronaut Sci"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1109\/DATE.2009.5090716"},{"year":"2012","author":"montesano","journal-title":"UVM Sequence Item Based Error Injection","key":"ref5"},{"key":"ref8","first-page":"271","article-title":"Fine particles, thin films and exchange anisotropy","volume":"iii","author":"jacobs","year":"1963","journal-title":"Magnetism"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1109\/DELTA.2008.36"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1007\/978-3-030-37277-4_59"},{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1109\/SpaceComp.2019.00008"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1109\/ICECS.2018.8617838"},{"doi-asserted-by":"publisher","key":"ref20","DOI":"10.1109\/IOLTS.2017.8046210"}],"event":{"name":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","start":{"date-parts":[[2020,10,19]]},"location":"Frascati, Italy","end":{"date-parts":[[2020,10,21]]}},"container-title":["2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9250742\/9250725\/09250871.pdf?arnumber=9250871","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,27]],"date-time":"2022-06-27T15:44:52Z","timestamp":1656344692000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9250871\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,10,19]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/dft50435.2020.9250871","relation":{},"subject":[],"published":{"date-parts":[[2020,10,19]]}}}