{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,26]],"date-time":"2025-11-26T16:38:23Z","timestamp":1764175103320,"version":"3.37.3"},"reference-count":22,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,10,6]],"date-time":"2021-10-06T00:00:00Z","timestamp":1633478400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,10,6]],"date-time":"2021-10-06T00:00:00Z","timestamp":1633478400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100004807","name":"DFG","doi-asserted-by":"publisher","award":["KR 3576\/29-2"],"award-info":[{"award-number":["KR 3576\/29-2"]}],"id":[{"id":"10.13039\/100004807","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,10,6]]},"DOI":"10.1109\/dft52944.2021.9568355","type":"proceedings-article","created":{"date-parts":[[2021,10,20]],"date-time":"2021-10-20T19:30:07Z","timestamp":1634758207000},"page":"1-6","source":"Crossref","is-referenced-by-count":2,"title":["A Tunable Single Event Transient Filter Based on Digitally Controlled Capacitive Delay Cells"],"prefix":"10.1109","author":[{"given":"Marko","family":"Andjelkovic","sequence":"first","affiliation":[{"name":"IHP - Leibniz-Institut für innovative Mikroelektronik,Frankfurt Oder,Germany"}]},{"given":"Oliver","family":"Schrape","sequence":"additional","affiliation":[{"name":"IHP - Leibniz-Institut für innovative Mikroelektronik,Frankfurt Oder,Germany"}]},{"given":"Anselm","family":"Breitenreiter","sequence":"additional","affiliation":[{"name":"IHP - Leibniz-Institut für innovative Mikroelektronik,Frankfurt Oder,Germany"}]},{"given":"Junchao","family":"Chen","sequence":"additional","affiliation":[{"name":"IHP - Leibniz-Institut für innovative Mikroelektronik,Frankfurt Oder,Germany"}]},{"given":"Milos","family":"Krstic","sequence":"additional","affiliation":[{"name":"IHP - Leibniz-Institut für innovative Mikroelektronik,Frankfurt Oder,Germany"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2018.8617996"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2006.60"},{"key":"ref12","article-title":"A Zero-Timing Overhead SET Mitigation Approach for Flash-Based FPGAs","author":"azimi","year":"0","journal-title":"Proc European Conf on Radiation and its Effects on Comp and Syst (RADECS) 2018"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2005.61"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2005.860719"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2006.884968"},{"key":"ref16","article-title":"A Tunable Soft-Error Filtering Circuit Based on Programmable- Threshold Inverters","author":"datta","year":"0","journal-title":"Proc Int Symp on Circuits and Systems (ISCAS)"},{"key":"ref17","article-title":"Applying Adaptive Temporal Filtering for SET Mitigation Based on Propagation-Delay of Every Logic Path","author":"souza","year":"0","journal-title":"Proc Latin-American Test Workshop (LATW)"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2006.886199"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2006.297681"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/23.903813"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2011.5784485"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.810787"},{"key":"ref5","article-title":"A Digitally Controlled Shunt Capacitor CMOS Delay Line","author":"adreani","year":"1999","journal-title":"Analog Integrated Circuits and Signal Processing"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2018.8617948"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt:20060111"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2014.6861093"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2002.1028924"},{"key":"ref9","article-title":"Use of Pass-Transistor Logic to Minimize the Impact of Soft Errors in Combinational Circuits","author":"kumar","year":"0","journal-title":"Proceedings of IEEE Workshop on Silicon Errors in Logic - System Effects"},{"key":"ref20","article-title":"Layout of Decoupling Capacitors in IP Blocks for 90-nm CMOS","author":"meng","year":"2008","journal-title":"IEEE Trans on VLSI Systems"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2009.2033798"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2007.910125"}],"event":{"name":"2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","start":{"date-parts":[[2021,10,6]]},"location":"Athens, Greece","end":{"date-parts":[[2021,10,8]]}},"container-title":["2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9568273\/9568279\/09568355.pdf?arnumber=9568355","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,8,3]],"date-time":"2022-08-03T00:07:24Z","timestamp":1659485244000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9568355\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,10,6]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/dft52944.2021.9568355","relation":{},"subject":[],"published":{"date-parts":[[2021,10,6]]}}}