{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,10]],"date-time":"2026-07-10T16:17:21Z","timestamp":1783700241622,"version":"3.55.0"},"reference-count":0,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,10,19]],"date-time":"2022-10-19T00:00:00Z","timestamp":1666137600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,10,19]],"date-time":"2022-10-19T00:00:00Z","timestamp":1666137600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,10,19]]},"DOI":"10.1109\/dft56152.2022.9962336","type":"proceedings-article","created":{"date-parts":[[2022,11,30]],"date-time":"2022-11-30T19:31:33Z","timestamp":1669836693000},"page":"1-6","source":"Crossref","is-referenced-by-count":9,"title":["HPMA-NTRU: High-Performance Polynomial Multiplication Accelerator for NTRU"],"prefix":"10.1109","author":[{"given":"Pengzhou","family":"He","sequence":"first","affiliation":[{"name":"Villanova University,Department of Electrical and Computer Engineering,Villanova,PA,USA,19087"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yazheng","family":"Tu","sequence":"additional","affiliation":[{"name":"Villanova University,Department of Electrical and Computer Engineering,Villanova,PA,USA,19087"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ayesha","family":"Khalid","sequence":"additional","affiliation":[{"name":"Queen’s University Belfast,Centre for Secure Information Technologies,Belfast,U.K."}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Maire","family":"O'Neill","sequence":"additional","affiliation":[{"name":"Queen’s University Belfast,Centre for Secure Information Technologies,Belfast,U.K."}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jiafeng","family":"Xie","sequence":"additional","affiliation":[{"name":"Villanova University,Department of Electrical and Computer Engineering,Villanova,PA,USA,19087"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","event":{"name":"2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","location":"Austin, TX, USA","start":{"date-parts":[[2022,10,19]]},"end":{"date-parts":[[2022,10,21]]}},"container-title":["2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9962319\/9962334\/09962336.pdf?arnumber=9962336","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,12,19]],"date-time":"2022-12-19T15:09:30Z","timestamp":1671462570000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9962336\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,10,19]]},"references-count":0,"URL":"https:\/\/doi.org\/10.1109\/dft56152.2022.9962336","relation":{},"subject":[],"published":{"date-parts":[[2022,10,19]]}}}