{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,22]],"date-time":"2025-10-22T05:24:18Z","timestamp":1761110658579},"reference-count":18,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,10,19]],"date-time":"2022-10-19T00:00:00Z","timestamp":1666137600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,10,19]],"date-time":"2022-10-19T00:00:00Z","timestamp":1666137600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,10,19]]},"DOI":"10.1109\/dft56152.2022.9962363","type":"proceedings-article","created":{"date-parts":[[2022,12,1]],"date-time":"2022-12-01T15:55:13Z","timestamp":1669910113000},"page":"1-7","source":"Crossref","is-referenced-by-count":1,"title":["INTERPLAY: An Intelligent Model for Predicting Performance Degradation due to Multi-cache Way-disabling"],"prefix":"10.1109","author":[{"given":"Panagiota","family":"Nikolaou","sequence":"first","affiliation":[{"name":"KIOS Centre of Excellence,Department of Electrical and Computer Engineering"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yiannakis","family":"Sazeides","sequence":"additional","affiliation":[{"name":"KIOS Centre of Excellence,Department of Electrical and Computer Engineering"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Maria K.","family":"Michael","sequence":"additional","affiliation":[{"name":"KIOS Centre of Excellence,Department of Electrical and Computer Engineering"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"Hot Chips 30 conference Fujitsu briefing","year":"2018","author":"fujitsu","key":"ref10"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/800046.801645"},{"key":"ref12","first-page":"48","article-title":"The performance vulnerability of architectural and non-architectural arrays to permanent faults","author":"hardy","year":"2012","journal-title":"IEEE Micro"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1007\/s11241-014-9212-x"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1061267.1061271"},{"key":"ref15","first-page":"151","article-title":"Exploiting choice in resizable cache design to optimize deep-submicron processor energy-delay","author":"yang","year":"2002","journal-title":"IEEE HPCA"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1007\/s11227-016-1927-0"},{"key":"ref17","article-title":"Sim-alpha: a validated execution driven alpha 21264 simulator","author":"desikan","year":"2001","journal-title":"Technical Report TR01-23 Tech Rep"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/605432.605403"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.22"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2014.2359572"},{"key":"ref6","first-page":"572","article-title":"Modeling the implications of dram failures and protection techniques on datacenter tco","author":"nikolaou","year":"2015","journal-title":"IEEE Micro"},{"journal-title":"Fault-Tolerant Systems","year":"2020","author":"koren","key":"ref5"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.892185"},{"journal-title":"Intel Itanium Processor 9700 Series Mission Critical Computing","year":"0","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1629915"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.21"},{"journal-title":"Cache Protection Mechanisms - IBM Power 595 Technical Overview And Introduction","year":"0","key":"ref9"}],"event":{"name":"2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","start":{"date-parts":[[2022,10,19]]},"location":"Austin, TX, USA","end":{"date-parts":[[2022,10,21]]}},"container-title":["2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9962319\/9962334\/09962363.pdf?arnumber=9962363","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,12,19]],"date-time":"2022-12-19T15:09:32Z","timestamp":1671462572000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9962363\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,10,19]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/dft56152.2022.9962363","relation":{},"subject":[],"published":{"date-parts":[[2022,10,19]]}}}