{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,26]],"date-time":"2025-11-26T19:04:28Z","timestamp":1764183868680,"version":"3.46.0"},"reference-count":53,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,10,21]],"date-time":"2025-10-21T00:00:00Z","timestamp":1761004800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,10,21]],"date-time":"2025-10-21T00:00:00Z","timestamp":1761004800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,10,21]]},"DOI":"10.1109\/dft66274.2025.11257462","type":"proceedings-article","created":{"date-parts":[[2025,11,25]],"date-time":"2025-11-25T18:27:02Z","timestamp":1764095222000},"page":"1-8","source":"Crossref","is-referenced-by-count":0,"title":["Special Session Paper: Application of Functional Verification Techniques in Hardware Trust"],"prefix":"10.1109","author":[{"given":"Mohammad Reza","family":"Heidari Iman","sequence":"first","affiliation":[{"name":"Univ. Grenoble Alpes,CNRS, Grenoble INP*, TIMA,,Grenoble,France,38000"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rolf","family":"Drechsler","sequence":"additional","affiliation":[{"name":"University of Bremen,Institute of Computer Science,Bremen,Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chandan Kumar","family":"Jha","sequence":"additional","affiliation":[{"name":"University of Bremen,Institute of Computer Science,Bremen,Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ali","family":"Azarpeyvand","sequence":"additional","affiliation":[{"name":"Tallinn University of Technology,Department of Computer Systems,Tallinn,Estonia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tara","family":"Ghasempouri","sequence":"additional","affiliation":[{"name":"Tallinn University of Technology,Department of Computer Systems,Tallinn,Estonia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sharjeel","family":"Imtiaz","sequence":"additional","affiliation":[{"name":"Tallinn University of Technology,Department of Computer Systems,Tallinn,Estonia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jaan","family":"Raik","sequence":"additional","affiliation":[{"name":"Tallinn University of Technology,Department of Computer Systems,Tallinn,Estonia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Samuele","family":"Germiniani","sequence":"additional","affiliation":[{"name":"University of Verona,Verona,Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Daniele","family":"Nicoletti","sequence":"additional","affiliation":[{"name":"University of Verona,Verona,Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Graziano","family":"Pravadelli","sequence":"additional","affiliation":[{"name":"University of Verona,Verona,Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Giorgio","family":"Di Natale","sequence":"additional","affiliation":[{"name":"Univ. Grenoble Alpes,CNRS, Grenoble INP*, TIMA,,Grenoble,France,38000"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1504\/IJES.2020.108861"},{"key":"ref2","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-031-90410-3","article-title":"Cham: Springer Nature Switzerland","author":"Iman","year":"2025","journal-title":"Advanced Techniques for Assertion-Based Verification in Hardware Designs Using Data Mining Algorithms"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2023.104773"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/DSD57027.2022.00095"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/NorCAS53631.2021.9599865"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS63720.2025.11006673"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.23919\/DATE64628.2025.10992895"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS63720.2025.11006802"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/b105236"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/307988.307989"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/3661308"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ATS64447.2024.10915489"},{"key":"ref13","first-page":"1","article-title":"Polynomial formal verification: Ensuring correctness under resource constraints","volume-title":"Proceedings of the 41st IEEE\/ACM International Conference on Computer-Aided Design","author":"Drechsler"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS52668.2021.9417052"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2021.3083682"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.23919\/DATE51398.2021.9474019"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.23919\/DATE58400.2024.10546775"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.23919\/DATE64628.2025.10992799"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1007\/11757283_5"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2001.915010"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/3716845"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/3716845"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2019.2958605"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8715138"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2024.3388256"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ETS61313.2024.10567242"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2024.3509013"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID64188.2025.00021"},{"key":"ref29","first-page":"1","article-title":"Large language models (llms) for verification, testing, and design","volume-title":"2025 ETS","author":"Jha","year":"2025"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ATS64447.2024.10915476"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/LAD62341.2024.10691874"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TIFS.2024.3372809"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/HLDVT.2017.8167465"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/3126552"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2022.3197525"},{"key":"ref36","first-page":"1","article-title":"A baseline framework for the qualification of Itl specification miners","author":"Germiniani","year":"2025","journal-title":"DATE"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-90410-3_5"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.23919\/date58400.2024.10546742"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-90410-3_4"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/NorCAS64408.2024.10752460"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-90410-3_6"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2022.102757"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.23919\/DATE58400.2024.10546519"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1145\/3604803"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2024.3449082"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/DSD51259.2020.00043"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS52668.2021.9417071"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS56072.2025.11043977"},{"journal-title":"PoC - Pile of Cores. Technische Universitat Dresden","article-title":"Chair of VLSI Design, Diagnostics and Architecture","year":"2016","key":"ref49"},{"volume-title":"Ibex risc-v core","key":"ref50","article-title":"PULP platform"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1145\/3214292.3214294"},{"key":"ref52","first-page":"159","article-title":"Formal verification of security properties on risc-v processors","author":"Chuah","year":"2023","journal-title":"2023 21st MEMOCODE"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI65124.2025.11130310"}],"event":{"name":"2025 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","start":{"date-parts":[[2025,10,21]]},"location":"Barcelona, Spain","end":{"date-parts":[[2025,10,23]]}},"container-title":["2025 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11253546\/11257433\/11257462.pdf?arnumber=11257462","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,11,26]],"date-time":"2025-11-26T19:00:34Z","timestamp":1764183634000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11257462\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,10,21]]},"references-count":53,"URL":"https:\/\/doi.org\/10.1109\/dft66274.2025.11257462","relation":{},"subject":[],"published":{"date-parts":[[2025,10,21]]}}}