{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T15:12:04Z","timestamp":1730214724607,"version":"3.28.0"},"reference-count":10,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/dftvs.2002.1173496","type":"proceedings-article","created":{"date-parts":[[2003,6,25]],"date-time":"2003-06-25T21:03:42Z","timestamp":1056575022000},"page":"3-11","source":"Crossref","is-referenced-by-count":4,"title":["Manufacturability analysis of analog CMOS ICs through examination of multiple layout solutions"],"prefix":"10.1109","author":[{"given":"P.","family":"Khademsameni","sequence":"first","affiliation":[]},{"given":"M.","family":"Syrzycki","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1147\/rd.276.0549"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/CCECE.2002.1015261"},{"journal-title":"VLSI Design for Manufacturing Yield Enhancement","year":"1989","author":"director","key":"ref10"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1999.748181"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1147\/rd.284.0461"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1985.1052403"},{"key":"ref7","first-page":"389","article-title":"New Techniques for Logic Fault Diagnosis with a Case Study on the 440BX Chipset","author":"venkataraman","year":"1999","journal-title":"Proc 25th ISTFA"},{"article-title":"Differential transmitters and Receivers for Very-High Frequency operation in a 0.25?m CMOS Technology","year":"2000","author":"henderson","key":"ref2"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1049\/el:19830156"},{"key":"ref1","first-page":"239","article-title":"Analysis of Manufacturability Factors for Analog CMOS A\/D converter Building Blocks","volume":"26","author":"ockey","year":"2001","journal-title":"Analog Integrated Circuits and Signal Processing International Journal"}],"event":{"name":"17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. DFT 2002","acronym":"DFTVS-02","location":"Vancouver, BC, Canada"},"container-title":["17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8374\/26363\/01173496.pdf?arnumber=1173496","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,13]],"date-time":"2017-03-13T18:25:43Z","timestamp":1489429543000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1173496\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/dftvs.2002.1173496","relation":{},"subject":[]}}