{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,22]],"date-time":"2025-03-22T08:41:38Z","timestamp":1742632898346},"reference-count":12,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/dftvs.2002.1173515","type":"proceedings-article","created":{"date-parts":[[2003,6,25]],"date-time":"2003-06-25T21:03:42Z","timestamp":1056575022000},"page":"186-194","source":"Crossref","is-referenced-by-count":8,"title":["Test time reduction in a manufacturing environment by combining BIST and ATE"],"prefix":"10.1109","author":[{"given":"H.","family":"Hashempour","sequence":"first","affiliation":[]},{"given":"F.J.","family":"Meyer","sequence":"additional","affiliation":[]},{"given":"F.","family":"Lombardi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/343647.343719"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2001.923409"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1993.590784"},{"key":"ref6","first-page":"237","article-title":"The Coverage Problem for Random Testing","author":"malaiya","year":"1984","journal-title":"Proc IEEE Intl Test Conf"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1987.1676905"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.2000.887168"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/EDAC.1991.206393"},{"key":"ref8","first-page":"220","article-title":"PREDICT-Probabilistic Estimation of Digital Circuit Testability","author":"seth","year":"1985","journal-title":"Proc IEEE Fault Tolerant Computer Symp (FTCS)"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/12.54854"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894198"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1990.129928"},{"article-title":"Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits","year":"2000","author":"bushnell","key":"ref1"}],"event":{"name":"17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. DFT 2002","acronym":"DFTVS-02","location":"Vancouver, BC, Canada"},"container-title":["17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8374\/26363\/01173515.pdf?arnumber=1173515","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,13]],"date-time":"2017-03-13T19:02:02Z","timestamp":1489431722000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1173515\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/dftvs.2002.1173515","relation":{},"subject":[]}}