{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,6]],"date-time":"2025-06-06T10:25:26Z","timestamp":1749205526452},"reference-count":20,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/dftvs.2002.1173517","type":"proceedings-article","created":{"date-parts":[[2003,6,26]],"date-time":"2003-06-26T01:03:42Z","timestamp":1056589422000},"page":"207-215","source":"Crossref","is-referenced-by-count":4,"title":["On-line testing of transient faults affecting functional blocks of FCMOS, domino and FPGA-implemented self-checking circuits"],"prefix":"10.1109","author":[{"given":"C.","family":"Metra","sequence":"first","affiliation":[]},{"given":"S.","family":"Di Francescantonio","sequence":"additional","affiliation":[]},{"given":"G.","family":"Marrale","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/43.644039"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1155\/2000\/42016"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1997.639653"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2001.966718"},{"key":"ref14","first-page":"948","article-title":"CMOS Checkers with Testable Bridging and Transistor Stuck-on Faults","author":"metra","year":"1992","journal-title":"Proc of Int Test Conf"},{"key":"ref15","first-page":"56","article-title":"Design of Self-Checking Combinational Circuits with Low Area Overhead","author":"saposhnikov","year":"1996","journal-title":"Proc IEEE Int On-Line Testing"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.1997.628336"},{"key":"ref17","first-page":"587","article-title":"On-Line Testing Scheme for Clocks' Faults","author":"metra","year":"1997","journal-title":"Proc of Int Test Conf"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/12.73583"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1993.313309"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1979.1675338"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1978.1675139"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/BF00136315"},{"key":"ref5","first-page":"245","article-title":"The Design of Strongly Fault-Secure and Strongly Code-Disjoint Combinational Circuits","author":"nanya","year":"1989","journal-title":"Proc Fault Tolerant Comput Symp"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/12.73584"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/43.46809"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1973.223705"},{"journal-title":"The 2001 National Technology Roadmap for Semiconductors","year":"2001","key":"ref1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1991.519520"},{"year":"0","key":"ref20"}],"event":{"name":"17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. DFT 2002","acronym":"DFTVS-02","location":"Vancouver, BC, Canada"},"container-title":["17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8374\/26363\/01173517.pdf?arnumber=1173517","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,13]],"date-time":"2017-03-13T22:08:31Z","timestamp":1489442911000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1173517\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/dftvs.2002.1173517","relation":{},"subject":[]}}