{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,22]],"date-time":"2025-03-22T08:41:30Z","timestamp":1742632890634},"reference-count":17,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/dftvs.2002.1173525","type":"proceedings-article","created":{"date-parts":[[2003,6,25]],"date-time":"2003-06-25T21:03:42Z","timestamp":1056575022000},"page":"284-292","source":"Crossref","is-referenced-by-count":7,"title":["Modeling of FPGA local\/global interconnect resources and derivation of minimal test configurations"],"prefix":"10.1109","author":[{"given":"X.","family":"Sun","sequence":"first","affiliation":[]},{"given":"A.","family":"Alimohammad","sequence":"additional","affiliation":[]},{"given":"P.","family":"Trouborst","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008396604722"},{"key":"ref11","first-page":"126","article-title":"Testing and Diagnosis of Interconnects using Boundary Scan","author":"hassan","year":"1985","journal-title":"Proc of IEEE International Test Conference"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1997.600278"},{"key":"ref13","doi-asserted-by":"crossref","DOI":"10.1145\/307418.307576","article-title":"Testing the Configurable Interconnect\/Logic Interface of SRAM-Based FPGA's","author":"renovell","year":"1999","journal-title":"Proceedings of the Design Automation and Test in Europe Conference and Exhibition"},{"journal-title":"The Programmable Logic Data Book","year":"2000","key":"ref14"},{"journal-title":"Computer Algorithms Introduction to Design & Analysis","year":"1993","author":"baase","key":"ref15"},{"key":"ref16","article-title":"An Algorithmic Method for Deriving Minimum TCs for FPGA Local Interconnects","author":"sun","year":"2002","journal-title":"Technical Report"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/CCECE.2002.1015263"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1996.510859"},{"key":"ref3","first-page":"100","article-title":"Diagnosing Programmable Interconnect Systems for FPGAs","author":"lombardi","year":"1996","journal-title":"Proc ACM\/SIGDA International Symposium on FPGAs"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.1996.555139"},{"key":"ref5","first-page":"125","article-title":"Testing the Interconnect Structure of Unconfigurated FPGA","author":"renovell","year":"1996","journal-title":"IEEE European Test Workshop"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1998.743180"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/54.655182"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1995.512646"},{"key":"ref1","first-page":"795","article-title":"Novel Technique for Built-In Self-Test of FPGA Interconnects","author":"sun","year":"2000","journal-title":"Proc of IEEE International Test Conference"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008376917755"}],"event":{"name":"17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. DFT 2002","acronym":"DFTVS-02","location":"Vancouver, BC, Canada"},"container-title":["17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8374\/26363\/01173525.pdf?arnumber=1173525","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,6,8]],"date-time":"2021-06-08T04:45:13Z","timestamp":1623127513000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1173525\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/dftvs.2002.1173525","relation":{},"subject":[]}}