{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T13:24:28Z","timestamp":1742390668243},"reference-count":19,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/dftvs.2002.1173530","type":"proceedings-article","created":{"date-parts":[[2003,6,25]],"date-time":"2003-06-25T21:03:42Z","timestamp":1056575022000},"page":"334-342","source":"Crossref","is-referenced-by-count":7,"title":["Adaptive test scheduling in SoC's by dynamic partitioning"],"prefix":"10.1109","author":[{"family":"Dan Zhao","sequence":"first","affiliation":[]},{"given":"S.","family":"Upadhyaya","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"178","article-title":"K2: an estimator for peak sustainable power of VLSI circuits","author":"hsiao","year":"1997","journal-title":"Proceedings of 1997 International Symposium on Low Power Electronics and Design LPE"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2001.990293"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2001.923464"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/92.929577"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/54.970423"},{"key":"ref15","first-page":"406","article-title":"Test scheduling in testable VLSI circuits","author":"kime","year":"1982","journal-title":"Proc Int l Symp Fault-Tolerant Computing"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2001.990292"},{"key":"ref17","article-title":"Test protocol scheduling for embedded-core based system ICs","author":"marinissen","year":"1998","journal-title":"2nd IEEE Int'l Workshop on TECS"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/IWRSP.2001.933855"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1993.313316"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/362342.362367"},{"key":"ref3","first-page":"695","article-title":"A neutral netlist of ten combinational benchmark circuits and a target simulator in fortran","author":"brglez","year":"1985","journal-title":"Intl Symp on Circuits and Systems"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/92.585217"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/43.875306"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1998.144279"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/12.2260"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1989.100747"},{"journal-title":"Graph Theory with Applications","year":"1977","author":"bondy","key":"ref1"},{"key":"ref9","first-page":"175","article-title":"Peak power estimation using genetic spot optimization for large VLSI circuits","author":"hsiao","year":"1999","journal-title":"Proceedings of the Design Automation and Test in Europe Conference"}],"event":{"name":"17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. DFT 2002","acronym":"DFTVS-02","location":"Vancouver, BC, Canada"},"container-title":["17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8374\/26363\/01173530.pdf?arnumber=1173530","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,13]],"date-time":"2017-03-13T17:13:07Z","timestamp":1489425187000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1173530\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/dftvs.2002.1173530","relation":{},"subject":[]}}