{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T03:07:36Z","timestamp":1729652856395,"version":"3.28.0"},"reference-count":17,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/dftvs.2002.1173533","type":"proceedings-article","created":{"date-parts":[[2003,6,25]],"date-time":"2003-06-25T21:03:42Z","timestamp":1056575022000},"page":"365-371","source":"Crossref","is-referenced-by-count":2,"title":["Emulation-based design errors identification"],"prefix":"10.1109","author":[{"given":"A.","family":"Castelnuovo","sequence":"first","affiliation":[]},{"given":"A.","family":"Fin","sequence":"additional","affiliation":[]},{"given":"F.","family":"Fummi","sequence":"additional","affiliation":[]},{"given":"F.","family":"Sforza","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2000.878268"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/23.983197"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.2000.887182"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2001.990301"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/43.790625"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2001.966704"},{"key":"ref16","first-page":"442","article-title":"Symbolic Functional Vector Generation for VHDL Specifications","author":"ferrandi","year":"1999","journal-title":"Proc IEEE Design Automation and Test in Europe Conference"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1016\/S1383-7621(01)00036-4"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.1998.655915"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/IJCNN.2001.939121"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"37","DOI":"10.1023\/A:1011193725824","article-title":"Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits","volume":"17","author":"keim","year":"2001","journal-title":"Journal of Electronic Testing"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/383251.383254"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2001.915055"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337611"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/92.920827"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/375977.376022"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/43.913758"}],"event":{"name":"17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. DFT 2002","acronym":"DFTVS-02","location":"Vancouver, BC, Canada"},"container-title":["17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8374\/26363\/01173533.pdf?arnumber=1173533","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,15]],"date-time":"2017-06-15T18:46:01Z","timestamp":1497552361000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1173533\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/dftvs.2002.1173533","relation":{},"subject":[]}}