{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,24]],"date-time":"2024-10-24T04:24:26Z","timestamp":1729743866518,"version":"3.28.0"},"reference-count":11,"publisher":"IEEE","license":[{"start":{"date-parts":[[2003,1,1]],"date-time":"2003-01-01T00:00:00Z","timestamp":1041379200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2003,1,1]],"date-time":"2003-01-01T00:00:00Z","timestamp":1041379200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2003]]},"DOI":"10.1109\/dftvs.2003.1250129","type":"proceedings-article","created":{"date-parts":[[2004,3,2]],"date-time":"2004-03-02T02:26:50Z","timestamp":1078194410000},"page":"336-343","source":"Crossref","is-referenced-by-count":6,"title":["Detailed comparison of dependability analyses performed at RT and gate levels"],"prefix":"10.1109","author":[{"given":"A.","family":"Ammari","sequence":"first","affiliation":[{"name":"TIMA Lab., Grenoble, France"}]},{"given":"R.","family":"Leveugle","sequence":"additional","affiliation":[{"name":"TIMA Lab., Grenoble, France"}]},{"given":"M.","family":"Sonza-Reorda","sequence":"additional","affiliation":[]},{"given":"M.","family":"Violante","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.2001.966775"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/OLT.2000.856614"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/OLT.2002.1030192"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.2000.887182"},{"year":"0","key":"ref11"},{"key":"ref5","article-title":"Multi-level fault injections in VHDL descriptions: alternative approaches and experiments","author":"leveugle","year":"0","journal-title":"appear in Journal of Electronic Testing Theory and Applications (JETTA)"},{"key":"ref8","first-page":"194","article-title":"Towards modeling for dependability of complex integrated circuits","author":"leveugle","year":"1999","journal-title":"IEEE International On-line Testing Workshop"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.2001.966777"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2002.998398"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2002.1039689"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/OLT.2002.1030194"}],"event":{"name":"Proceedings. 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","start":{"date-parts":[[2003,11,5]]},"location":"Boston, MA, USA","end":{"date-parts":[[2003,11,5]]}},"container-title":["Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8839\/27973\/01250129.pdf?arnumber=1250129","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T17:46:23Z","timestamp":1729705583000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/1250129\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/dftvs.2003.1250129","relation":{},"subject":[],"published":{"date-parts":[[2003]]}}}