{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T09:29:15Z","timestamp":1725442155646},"reference-count":19,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/dftvs.2003.1250140","type":"proceedings-article","created":{"date-parts":[[2004,3,1]],"date-time":"2004-03-01T21:26:50Z","timestamp":1078176410000},"page":"425-432","source":"Crossref","is-referenced-by-count":2,"title":["Control constrained resource partitioning for complex SoCs [intra-chip wireless interconnects]"],"prefix":"10.1109","author":[{"given":"D.","family":"Zhao","sequence":"first","affiliation":[]},{"given":"S.","family":"Upadhyaya","sequence":"additional","affiliation":[]},{"given":"M.","family":"Margala","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","article-title":"A geometric theorem for wireless network design optimization","author":"franceschetti","year":"2002","journal-title":"Lee Center Advanced Network Workshop"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2455.214106"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2001.990293"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2001.966728"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2001.990292"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.1992.224417"},{"key":"ref16","article-title":"An ILP formulation to optimize test access mechanism","author":"nourani","year":"0","journal-title":"Proc of ITC'2000"},{"key":"ref17","article-title":"Adaptive test scheduling in SoCs by dynamic partitioning","author":"zhao","year":"2002","journal-title":"IEEE Int Symp Defect Fault Tolerance VLSI Syst"},{"key":"ref18","article-title":"Power constrained test scheduling with dynamically varied TAM","author":"zhao","year":"2003","journal-title":"IEEE VLSI Test Symposium"},{"key":"ref19","first-page":"90","article-title":"A new distributed test control architecture with multihop wireless test connectivity and communication for gigahertz system-on-chips","author":"zhao","year":"2003","journal-title":"Proc NATW"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1287\/moor.4.3.233"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/5.920578"},{"article-title":"A CMOS wireless interconnect system for multigigahertz clock distribution","year":"2001","author":"floyd","key":"ref6"},{"article-title":"Introduction to Algorithms","year":"2001","author":"cormen","key":"ref5"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1016\/0020-0190(81)90111-3"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/4.997846"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/43.875306"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.2000.843836"},{"key":"ref9","article-title":"A geometric theorem for approximate disk covering algorithms","author":"franceschetti","year":"2001","journal-title":"Paradise Technical Report ETR035"}],"event":{"name":"18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","acronym":"DFTVS-03","location":"Boston, MA, USA"},"container-title":["Proceedings. 16th IEEE Symposium on Computer Arithmetic"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8839\/27973\/01250140.pdf?arnumber=1250140","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,13]],"date-time":"2017-03-13T14:43:37Z","timestamp":1489416217000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1250140\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/dftvs.2003.1250140","relation":{},"subject":[]}}