{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T03:46:26Z","timestamp":1725421586764},"reference-count":17,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/dftvs.2003.1250155","type":"proceedings-article","created":{"date-parts":[[2004,3,1]],"date-time":"2004-03-01T21:26:50Z","timestamp":1078176410000},"page":"555-562","source":"Crossref","is-referenced-by-count":8,"title":["An integrated fault-tolerant design framework for VLIW processors"],"prefix":"10.1109","author":[{"family":"Yung-Yuan Chen","sequence":"first","affiliation":[]},{"family":"Shi-Jinn Horng","sequence":"additional","affiliation":[]},{"family":"Hung-Chuan Lai","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/HIPC.1996.565839"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/40.877951"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICDSN.2000.857579"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ICDSN.2000.857578"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2001.941424"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/PRDC.2001.992702"},{"key":"ref16","first-page":"27","article-title":"SSD: An Affordable Fault Tolerant Architecture for Superscalar Processors","author":"kim","year":"2001","journal-title":"Proc Pacific Rim Int l Symp Dependable Computing"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.2001.966766"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2002.1028901"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.1998.678193"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.1992.224418"},{"key":"ref5","first-page":"436","article-title":"A Study of Time-Redundant Fault Tolerance Techniques for High-Performance Pipelined Processors","author":"sohi","year":"1989","journal-title":"Proc 19th FTCS"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/FTCS.1995.466952"},{"key":"ref7","first-page":"192","article-title":"Low Cost Concurrent Error Detection in A VLIW Architecture Using Replicated Instructions","author":"holm","year":"1992","journal-title":"Int Conf on Parallel Processing"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/40.877947"},{"key":"ref1","article-title":"COMPUTER ARCHITECTURE A QUANTITATIVE APPROACH","author":"patterson","year":"0","journal-title":"MORGAN KAUFMANN 1996"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.1995.476954"}],"event":{"name":"18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","acronym":"DFTVS-03","location":"Boston, MA, USA"},"container-title":["Proceedings. 16th IEEE Symposium on Computer Arithmetic"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8839\/27973\/01250155.pdf?arnumber=1250155","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,13]],"date-time":"2017-03-13T15:19:31Z","timestamp":1489418371000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1250155\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/dftvs.2003.1250155","relation":{},"subject":[]}}