{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,1]],"date-time":"2025-11-01T21:26:58Z","timestamp":1762032418550,"version":"3.28.0"},"reference-count":17,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/dsd.2002.1115345","type":"proceedings-article","created":{"date-parts":[[2003,6,25]],"date-time":"2003-06-25T21:03:42Z","timestamp":1056575022000},"page":"4-11","source":"Crossref","is-referenced-by-count":2,"title":["An asynchronous victim cache"],"prefix":"10.1109","author":[{"given":"D.","family":"Hormdee","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.D.","family":"Garside","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S.B.","family":"Furber","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1990.134547"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1993.698560"},{"key":"ref12","first-page":"81","article-title":"Lockup-free instruction fetch\/prefetch cache organization","author":"kroft","year":"1981","journal-title":"Proc Int Symp Computer Architecture (ISCA‘81)"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ARVLSI.1997.634853"},{"key":"ref14","article-title":"A Cache Line Fill Circuit for a Micropipelined Asynchronous Microprocessor","author":"mehra","year":"1995","journal-title":"IEEE Technical Committee on Computer Architecture Newsletter"},{"key":"ref15","article-title":"Efects of Main Memory Latencies on the Performance of Non-blocking Caches","author":"\u00f6nerand","year":"1992","journal-title":"Technical Report #CENG-92–34"},{"key":"ref16","article-title":"System Timing","author":"seitz","year":"1980","journal-title":"Chapter 7 of Introduction to VLSI Systems"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1997.628881"},{"key":"ref4","first-page":"162","article-title":"AMULET3i-an Asynchronous System-on-Chip","author":"garside","year":"2000","journal-title":"Proc Int Symp Advanced Research in Asynchronous Circuits and Systems"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/5.740018"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.1997.587137"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.1996.494452"},{"key":"ref8","article-title":"Design Decisions for SPUR","volume":"19","author":"hill","year":"1986","journal-title":"IEEE Computer"},{"article-title":"ComputerArchitecture: A Quantitative Approach","year":"1996","author":"hennessy","key":"ref7"},{"article-title":"LARD Documentation Home Page","year":"0","author":"endecott","key":"ref2"},{"year":"2000","key":"ref1","article-title":"ARM Architecture Reference Manual"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2001.914079"}],"event":{"name":"Euromicro Symposium on Digital System Design. DSD'2002","acronym":"DSD-02","location":"Dortmund, Germany"},"container-title":["Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8187\/24597\/01115345.pdf?arnumber=1115345","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,13]],"date-time":"2017-03-13T17:26:35Z","timestamp":1489425995000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1115345\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/dsd.2002.1115345","relation":{},"subject":[]}}