{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,3]],"date-time":"2024-09-03T20:36:55Z","timestamp":1725395815694},"reference-count":19,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/dsd.2002.1115367","type":"proceedings-article","created":{"date-parts":[[2003,6,26]],"date-time":"2003-06-26T01:03:42Z","timestamp":1056589422000},"page":"180-186","source":"Crossref","is-referenced-by-count":0,"title":["Using formal tools to study complex circuits behaviour"],"prefix":"10.1109","author":[{"given":"P.","family":"Amblard","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"F.","family":"Lagnier","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Levy","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"89","article-title":"Proving the Correctness of Pipelined Micro-Architectures","author":"kroening","year":"2000","journal-title":"Proc ITG\/GI\/GMM Workshop"},{"key":"ref11","first-page":"558","author":"levitt","year":"1996","journal-title":"A Scalable Formal Verifcation Methodology for Pipelined Microprocessors DAC 1996"},{"key":"ref12","first-page":"219","article-title":"Verifcation of Infnite State Systems by Compositional Model Checking","author":"mcmillan","year":"1999","journal-title":"CHARME 1999 Bad Herrenhalb"},{"journal-title":"SPARC Architecture Assembly Language Programming and C","year":"1994","author":"paul","key":"ref13"},{"key":"ref14","first-page":"156","article-title":"Hardware Verification using PVS, Formal Hardware Verifcation","author":"srivas","year":"1997"},{"journal-title":"Digital Circuit Design","year":"1995","author":"wirth","key":"ref15"},{"journal-title":"The SPARC Architecture Manual Version 8","year":"1992","key":"ref16"},{"year":"0","key":"ref17"},{"year":"0","key":"ref18"},{"year":"0","key":"ref19"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-5651-0_30"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"261","DOI":"10.1007\/978-94-015-9506-3_60","article-title":"Introducing Digital Circuits Design and Verifcation Concurrently","author":"amblard","year":"2000","journal-title":"Proceedings of the 3rd European Workshop on Microelectronics Education Aix en Provence"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-2231-4"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1016\/0167-6423(92)90018-7"},{"key":"ref8","first-page":"785","article-title":"Programming and Verifying Real-time Systems by Means of the Synchronous Data-fb w Programming Language Lustre","author":"halbwachs","year":"1992","journal-title":"IEEE Transactions on Software Engineering Special Issue on the Specifcation and Analysis of Real-Time Systems"},{"key":"ref7","doi-asserted-by":"crossref","first-page":"1305","DOI":"10.1109\/5.97300","article-title":"The Synchronous Data-fb w Programming Language Lustre","author":"halbwachs","year":"1991","journal-title":"Proceedings of the IEEE"},{"journal-title":"Architectures Logicielles et Mat&#x00E9;rielles Dunod","year":"2000","author":"amblard","key":"ref2"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/40.768501"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"443","DOI":"10.1109\/12.859539","article-title":"AQUILA: An Equivalence Checking System for Large Sequential Designs","author":"huang","year":"2000","journal-title":"IEEE Transactions on Computers"}],"event":{"name":"Euromicro Symposium on Digital System Design. DSD'2002","acronym":"DSD-02","location":"Dortmund, Germany"},"container-title":["Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8187\/24597\/01115367.pdf?arnumber=1115367","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,3,24]],"date-time":"2020-03-24T02:47:52Z","timestamp":1585018072000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1115367\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/dsd.2002.1115367","relation":{},"subject":[]}}