{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T15:13:47Z","timestamp":1730214827635,"version":"3.28.0"},"reference-count":12,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/dsd.2002.1115396","type":"proceedings-article","created":{"date-parts":[[2003,6,25]],"date-time":"2003-06-25T21:03:42Z","timestamp":1056575022000},"page":"385-392","source":"Crossref","is-referenced-by-count":0,"title":["Bit-level allocation of multiple-precision specifications"],"prefix":"10.1109","author":[{"given":"M.C.","family":"Molina","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.M.","family":"Mendias","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"R.","family":"Hermida","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","article-title":"System-level fixed-point design based on an interpolative approach","author":"willens","year":"0","journal-title":"Proc DAC 1997"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/SIPS.1998.715819"},{"key":"ref10","article-title":"Low-power behavioural synthesis optimization using multiple precision arithmetic","author":"ercegovac","year":"1999","journal-title":"Proc DAC"},{"key":"ref6","article-title":"Data Path tradeoffs using MABAL","author":"k\u00fcakar","year":"1990","journal-title":"Proc ACM\/IEEE DAC"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2001.915122"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/123186.123350"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.1997.568070"},{"key":"ref8","article-title":"OSCAR: Optimum simultaneous scheduling, allocation and resource binding based on integer programming","author":"landwehr","year":"1994","journal-title":"Proc EDAC"},{"key":"ref7","first-page":"379","article-title":"Data path construction and refinement","volume":"cad 5","author":"tsai","year":"1986","journal-title":"Proc ICCDCS"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.2000.903430"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-44614-1_69"},{"key":"ref1","article-title":"A methodology and design environment for DSP ASIC fixed point refinement","author":"cmar","year":"1999","journal-title":"Proc DATE M&#x00FC;nchen"}],"event":{"name":"Euromicro Symposium on Digital System Design. DSD'2002","acronym":"DSD-02","location":"Dortmund, Germany"},"container-title":["Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8187\/24597\/01115396.pdf?arnumber=1115396","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,13]],"date-time":"2017-03-13T17:37:21Z","timestamp":1489426641000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1115396\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/dsd.2002.1115396","relation":{},"subject":[]}}