{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T18:56:14Z","timestamp":1725562574537},"reference-count":9,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2003]]},"DOI":"10.1109\/dsd.2003.1231902","type":"proceedings-article","created":{"date-parts":[[2004,3,22]],"date-time":"2004-03-22T09:34:28Z","timestamp":1079948068000},"page":"70-75","source":"Crossref","is-referenced-by-count":0,"title":["DYNORA: a new caching technique"],"prefix":"10.1109","author":[{"given":"P.","family":"Srivatsan","sequence":"first","affiliation":[]},{"given":"P.B.","family":"Sudarshan","sequence":"additional","affiliation":[]},{"given":"P.P.","family":"Bhaskaran","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","article-title":"Dynamic cache partitioning via columnization. Memo 430","author":"chiou","year":"2000","journal-title":"Computer Systems Group"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/224081.224093"},{"journal-title":"Computer Architecture A Quantitative Approach","year":"1996","author":"henessey","key":"ref6"},{"key":"ref5","first-page":"248","article-title":"Selective cache ways: On-demand resource allocation","author":"albonesi","year":"2000","journal-title":"Proc 32nd Annu IEEE\/ACM Int Symp Microarchitecture (MICRO 32)"},{"key":"ref8","article-title":"Highly associative caches for low power processors","author":"zhang","year":"2001","journal-title":"Proceedings of 33rd International Symposium on Micro-Architecture"},{"article-title":"High-Performance Low power Cache Architectures","year":"2000","author":"inoue","key":"ref7"},{"key":"ref2","article-title":"Exploiting choice in resizable cache design to optimize deep-submicron processor energy-delay","author":"se-hyun","year":"2001","journal-title":"Eighth International Symposium on High-Performance Computer Architecture"},{"key":"ref9","article-title":"Energy optimization for multilevel cache architectures for rise and cisc processors","author":"ko","year":"1998","journal-title":"Proceedings of the international symposium on Low power electronics and design"},{"key":"ref1","article-title":"An integrated circuit\/architecture approach to reducing leakage in deep-submicron high-performance i-caches","author":"falsafi","year":"2000","journal-title":"Proc Seventh Int l Symp High Performance Computer Architecture (HPCA)"}],"event":{"name":"Proceedings. Euromicro Symposium on Digital System Design","start":{"date-parts":[[2003,9,1]]},"location":"Belek-Antalya, Turkey","end":{"date-parts":[[2003,9,6]]}},"container-title":["Euromicro Symposium on Digital System Design, 2003. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8715\/27588\/01231902.pdf?arnumber=1231902","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,13]],"date-time":"2017-03-13T20:10:30Z","timestamp":1489435830000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1231902\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/dsd.2003.1231902","relation":{},"subject":[],"published":{"date-parts":[[2003]]}}}