{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,3]],"date-time":"2024-09-03T20:39:11Z","timestamp":1725395951019},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2003]]},"DOI":"10.1109\/dsd.2003.1231935","type":"proceedings-article","created":{"date-parts":[[2004,3,22]],"date-time":"2004-03-22T09:34:28Z","timestamp":1079948068000},"page":"240-247","source":"Crossref","is-referenced-by-count":0,"title":["Back-end dynamic resource allocation heuristics for power-aware high-performance clustered architectures"],"prefix":"10.1109","author":[{"given":"A.","family":"Baniasadi","sequence":"first","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"crossref","DOI":"10.1145\/279361.279377","article-title":"Pipeline Gating: Speculation Control For Energy Reduction","author":"manne","year":"1998","journal-title":"Proc International Symposium on Computer Architecture"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1998.694768"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/383082.383088"},{"key":"ref13","article-title":"The Alpha 21264 architecture","author":"kessler","year":"1998","journal-title":"Proc of International Conference on Computer Design"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/368122.368807"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2001.937452"},{"key":"ref6","first-page":"83","article-title":"Wattch: a framework for architectural-level power analysis and optimizations","author":"brooks","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"ref5","article-title":"Reducing Power Requirements of Instruction Scheduling Through Dynamic Allocation of Multiple Datapath Resources","author":"ponomarev","year":"2002","journal-title":"Proc 34th Int l Symp Microarchitecture"},{"key":"ref8","article-title":"Quantifing the complexity of superscalar processors","author":"palacharla","year":"1996","journal-title":"Technical Report CS-TR-96&#x2013;1308"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/268806.268810"},{"key":"ref2","article-title":"Run-time Scaling of Microarchitecture Resources in a Processor for Energy Savings","author":"iyer","year":"2000","journal-title":"Proc Kool Chips Workshop Held Conjunction With MICRO-33"},{"key":"ref1","article-title":"An Adaptive Issue Queue for Reduced Power at High Performance","author":"buyuktosunoglu","year":"2000","journal-title":"Workshop on Power-Aware Computers Systems held in conjunction with ASPLOS"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1997.604689"}],"event":{"name":"Proceedings. Euromicro Symposium on Digital System Design","start":{"date-parts":[[2003,9,1]]},"location":"Belek-Antalya, Turkey","end":{"date-parts":[[2003,9,6]]}},"container-title":["Euromicro Symposium on Digital System Design, 2003. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8715\/27588\/01231935.pdf?arnumber=1231935","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T00:26:33Z","timestamp":1497572793000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1231935\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/dsd.2003.1231935","relation":{},"subject":[],"published":{"date-parts":[[2003]]}}}