{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,8]],"date-time":"2026-02-08T07:47:24Z","timestamp":1770536844873,"version":"3.49.0"},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007,8]]},"DOI":"10.1109\/dsd.2007.4341456","type":"proceedings-article","created":{"date-parts":[[2007,10,9]],"date-time":"2007-10-09T13:45:59Z","timestamp":1191937559000},"page":"102-108","source":"Crossref","is-referenced-by-count":10,"title":["An efficient and optimized FPGA Feedback M-PSK Symbol Timing Recovery Architecture based on the Gardner Timing Error Detector"],"prefix":"10.1109","author":[{"given":"Emanuele","family":"Sciagura","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Paolo","family":"Zicari","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Stefania","family":"Perri","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pasquale","family":"Corsonello","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","first-page":"312","article-title":"Optimal Design and Simulation for Multi.-rate Symbol Timing Recovery in Software Radio QPSK Demodulation","author":"wei","year":"2004","journal-title":"IEEE 3rd ICCEA"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.2000.903406"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.2002.1196948"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICC.1996.541273"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/26.293686"},{"key":"ref8","article-title":"An Efficient Circuit for Bit-Detection and Timing Recovery Using FPGAs","author":"zicari","year":"2006","journal-title":"Proc of the 13th IEEE International Conference on Electronics Circuits and Systems - ICECS'06"},{"key":"ref7","article-title":"Digital Communications","author":"proakis","year":"0"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCOM.1976.1093326"},{"key":"ref9","first-page":"1402","article-title":"High speed all digital symbol timing recovery based on FPGA","volume":"2","author":"jian","year":"2005","journal-title":"Proc of International Conference on Wireless Communications Networking and Mobile Computing"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCOM.1986.1096561"}],"event":{"name":"10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)","location":"Lubeck, Germany","start":{"date-parts":[[2007,8,29]]},"end":{"date-parts":[[2007,8,31]]}},"container-title":["10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4341432\/4341433\/04341456.pdf?arnumber=4341456","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,16]],"date-time":"2017-03-16T13:54:16Z","timestamp":1489672456000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4341456\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,8]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/dsd.2007.4341456","relation":{},"subject":[],"published":{"date-parts":[[2007,8]]}}}