{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T22:33:07Z","timestamp":1729636387499,"version":"3.28.0"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007,8]]},"DOI":"10.1109\/dsd.2007.4341478","type":"proceedings-article","created":{"date-parts":[[2007,10,9]],"date-time":"2007-10-09T17:45:59Z","timestamp":1191951959000},"page":"261-264","source":"Crossref","is-referenced-by-count":2,"title":["Power Estimation of Time Variant SoCs with TAPES"],"prefix":"10.1109","author":[{"given":"Andreas","family":"Lankes","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Thomas","family":"Wild","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Johannes","family":"Zeppenfeld","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1109\/MDT.2002.1047740"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"173","DOI":"10.1145\/280756.280881","article-title":"System-level power estimation and optimization","author":"benini","year":"1998","journal-title":"Proceedings 1998 International Symposium on Low Power Electronics and Design (IEEE Cat No 98TH8379) LPE"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1109\/ISSS.2000.874044"},{"key":"ref13","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1117\/12.585564","article-title":"Instruction Level Power Dissipation in the Intel XScale Embedded Processor","author":"varma","year":"2005","journal-title":"Embedded Processors For Multimedia and Communications II"},{"doi-asserted-by":"publisher","key":"ref14","DOI":"10.1109\/WWC.2003.1249056"},{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1016\/S0167-9260(04)00032-X"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"157","DOI":"10.1007\/s10617-006-9589-4","article-title":"TAPES-Trace-based architecture performance evaluation with SystemC","volume":"10","author":"wild","year":"2006","journal-title":"Design Automation for Embedded Systems"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1049\/ip-cdt:20045088"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1007\/11603009_1"},{"year":"0","journal-title":"SystemC Homepage","key":"ref8"},{"key":"ref7","article-title":"Transaction Level Modeling: An Overview","author":"cai","year":"2003","journal-title":"Proc CODES + ISSS"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1109\/ICAC.2005.61"},{"year":"1997","author":"raghunathan","article-title":"High-level power analysis and optimization","key":"ref1"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1145\/1016720.1016742"}],"event":{"name":"10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)","start":{"date-parts":[[2007,8,29]]},"location":"Lubeck, Germany","end":{"date-parts":[[2007,8,31]]}},"container-title":["10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4341432\/4341433\/04341478.pdf?arnumber=4341478","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,17]],"date-time":"2017-06-17T23:46:25Z","timestamp":1497743185000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4341478\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,8]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/dsd.2007.4341478","relation":{},"subject":[],"published":{"date-parts":[[2007,8]]}}}