{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T18:15:13Z","timestamp":1725560113452},"reference-count":18,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007,8]]},"DOI":"10.1109\/dsd.2007.4341482","type":"proceedings-article","created":{"date-parts":[[2007,10,9]],"date-time":"2007-10-09T17:45:59Z","timestamp":1191951959000},"page":"288-295","source":"Crossref","is-referenced-by-count":2,"title":["Graph Matching Constraints for Synthesis with Complex Components"],"prefix":"10.1109","author":[{"given":"Ana Fuentes","family":"Martinez","sequence":"first","affiliation":[]},{"given":"Krzysztof","family":"Kuchcinski","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/605440.605446"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/785411.785416"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1017\/S0960129501003577"},{"key":"ref13","doi-asserted-by":"crossref","DOI":"10.7551\/mitpress\/5625.001.0001","article-title":"Programming with Constraints: an Introduction","author":"marriott","year":"1998"},{"key":"ref14","doi-asserted-by":"crossref","first-page":"604","DOI":"10.1145\/775832.775985","article-title":"Global resource sharing for synthesis of control data flow graphs on FPGAs","author":"memik","year":"2003","journal-title":"DAC '03 Proc of the 40th Conference on Design Automation"},{"journal-title":"Handbook of Constraint Programming","year":"2006","author":"rossi","key":"ref15"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/502175.502181"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2007.4430001"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2006.75"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2005.1560122"},{"key":"ref3","first-page":"41","article-title":"Improvements to technology mapping for LUT-based FP-GAs","author":"chatterjee","year":"2006","journal-title":"Proceedings of the internation symposium on Field programmable gate arrays - FPGA'06"},{"article-title":"Achieving higher system performance with the Virtex-5 family of FP-GAs","year":"2006","author":"cosoroaba","key":"ref6"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1117201.1117207"},{"article-title":"Computers and Intractability: A Guide to the Theory of NP-Completeness","year":"1979","author":"garey","key":"ref8"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/11564751_18"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"413","DOI":"10.1145\/157485.164956","article-title":"high-level transformations for minimizing syntactic variances","author":"chaiyakul","year":"1993","journal-title":"30th ACM\/IEEE Design Automation Conference"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1120725.1120791"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1137\/0202019"}],"event":{"name":"10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)","start":{"date-parts":[[2007,8,29]]},"location":"Lubeck, Germany","end":{"date-parts":[[2007,8,31]]}},"container-title":["10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4341432\/4341433\/04341482.pdf?arnumber=4341482","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,8,25]],"date-time":"2021-08-25T13:54:32Z","timestamp":1629899672000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4341482\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,8]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/dsd.2007.4341482","relation":{},"subject":[],"published":{"date-parts":[[2007,8]]}}}