{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,29]],"date-time":"2025-08-29T00:06:23Z","timestamp":1756425983640,"version":"3.44.0"},"reference-count":23,"publisher":"IEEE","license":[{"start":{"date-parts":[[2008,6,1]],"date-time":"2008-06-01T00:00:00Z","timestamp":1212278400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2008,6,1]],"date-time":"2008-06-01T00:00:00Z","timestamp":1212278400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,6]]},"DOI":"10.1109\/dsn.2008.4630095","type":"proceedings-article","created":{"date-parts":[[2008,9,26]],"date-time":"2008-09-26T11:10:29Z","timestamp":1222427429000},"page":"267-276","source":"Crossref","is-referenced-by-count":5,"title":["A fault-tolerant directory-based cache coherence protocol for CMP architectures"],"prefix":"10.1109","author":[{"given":"Ricardo","family":"Fernandez-Pascual","sequence":"first","affiliation":[{"name":"Universidad de Murcia, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jose M.","family":"Garcia","sequence":"additional","affiliation":[{"name":"Universidad de Murcia, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Manuel E.","family":"Acacio","sequence":"additional","affiliation":[{"name":"Universidad de Murcia, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jose","family":"Duato","sequence":"additional","affiliation":[{"name":"Universidad Polit\u00e9cnica de Valencia, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003567"},{"key":"22","doi-asserted-by":"crossref","first-page":"24","DOI":"10.1109\/ISCA.1995.524546","article-title":"The SPLASH-2 programs: characterization and methodological considerations","author":"woo","year":"1995","journal-title":"Proceedings 22nd Annual International Symposium on Computer Architecture ISCA"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2006.35"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.53"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2004.1339507"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.37"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.104"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2006.29"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346193"},{"key":"11","doi-asserted-by":"crossref","first-page":"92","DOI":"10.1145\/1105734.1105747","article-title":"multifacet's general execution-driven multiprocessor simulator (gems) toolset","volume":"33","author":"martin","year":"2005","journal-title":"Computer Architecture News"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250670"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2002.997877"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.69"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003568"},{"key":"2","first-page":"282","article-title":"Piranha: a scalable architecture based on single-chip multiprocessing","author":"barroso","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250720"},{"key":"10","doi-asserted-by":"crossref","first-page":"182","DOI":"10.1145\/871656.859640","article-title":"token coherence: decoupling performance and correctness","author":"martin","year":"2003","journal-title":"The 30th Annual International Symp on Computer Architecture"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346194"},{"article-title":"a fault-tolerant directory-based cache coherence protocol for shared-memory architectures","year":"2007","author":"ferna?ndez-pascual","key":"6"},{"key":"5","first-page":"225","article-title":"towards onchip fault-tolerant communication","author":"dumitras","year":"2003","journal-title":"ASPDAC Proceedings of the 2003 conference on Asia South Pacific Design Automation"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2006.1598108"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/2.982916"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/40.848474"}],"event":{"name":"2008 IEEE International Conference on Dependable Systems & Networks With FTCS and DCC (DSN)","start":{"date-parts":[[2008,6,24]]},"location":"Anchorage, AK, USA","end":{"date-parts":[[2008,6,27]]}},"container-title":["2008 IEEE International Conference on Dependable Systems and Networks With FTCS and DCC (DSN)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4610267\/4630050\/04630095.pdf?arnumber=4630095","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,28]],"date-time":"2025-08-28T18:03:14Z","timestamp":1756404194000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/4630095\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,6]]},"references-count":23,"URL":"https:\/\/doi.org\/10.1109\/dsn.2008.4630095","relation":{},"subject":[],"published":{"date-parts":[[2008,6]]}}}