{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T23:05:21Z","timestamp":1747868721871,"version":"3.37.3"},"reference-count":21,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,6]]},"DOI":"10.1109\/dsn.2010.5544278","type":"proceedings-article","created":{"date-parts":[[2010,8,10]],"date-time":"2010-08-10T20:44:07Z","timestamp":1281473047000},"page":"487-496","source":"Crossref","is-referenced-by-count":6,"title":["A unified model for timing speculation: Evaluating the impact of technology scaling, CMOS design style, and fault recovery mechanism"],"prefix":"10.1109","author":[{"given":"Marc","family":"de Kruijf","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shuou","family":"Nomura","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Karthikeyan","family":"Sankaralingam","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.852295"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2008.4672038"},{"key":"ref12","article-title":"CMOS process variations: A critical operation point hypothesis","author":"patel","year":"2008","journal-title":"Online Presentation"},{"key":"ref13","doi-asserted-by":"crossref","DOI":"10.1007\/978-0-387-71713-5","author":"rabaey","year":"2009","journal-title":"Low Power Design Essentials"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TSM.2007.913186"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771810"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.42"},{"key":"ref17","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-031-01723-0","author":"sorin","year":"2009","journal-title":"Fault Tolerant Computer Architecture"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003559"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.803949"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798256"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253179"},{"key":"ref6","article-title":"45nm Transistor Reliability","volume":"12","author":"hicks","year":"2008","journal-title":"Intel Technology Journal"},{"key":"ref5","first-page":"213","article-title":"Paceline: Improving single-thread performance in nanoscale CMPs through core over-clocking","author":"greskamp","year":"0","journal-title":"PACT '07"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2005.43"},{"journal-title":"Enhanced Intel SpeedStep Technology for the Intel Pentium M Processor","year":"2004","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1816026"},{"journal-title":"International Technology Roadmap for Semiconductors","article-title":"Process integration, devices, and structures","year":"2008","key":"ref1"},{"key":"ref9","article-title":"A systematic methodology to compute the architectural vulnerability factors for a highperformance microprocessor","author":"mukherjee","year":"0","journal-title":"MICRO '03"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687430"},{"journal-title":"Subthreshold Design for Ultra Low-Power Systems","year":"2006","author":"wang","key":"ref21"}],"event":{"name":"Networks (DSN)","start":{"date-parts":[[2010,6,28]]},"location":"Chicago, IL, USA","end":{"date-parts":[[2010,7,1]]}},"container-title":["2010 IEEE\/IFIP International Conference on Dependable Systems & Networks (DSN)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5532324\/5544245\/05544278.pdf?arnumber=5544278","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,24]],"date-time":"2025-02-24T02:33:16Z","timestamp":1740364396000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5544278\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,6]]},"references-count":21,"URL":"https:\/\/doi.org\/10.1109\/dsn.2010.5544278","relation":{},"subject":[],"published":{"date-parts":[[2010,6]]}}}