{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,30]],"date-time":"2025-12-30T17:49:35Z","timestamp":1767116975916},"reference-count":33,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,6]]},"DOI":"10.1109\/dsn.2010.5544918","type":"proceedings-article","created":{"date-parts":[[2010,8,10]],"date-time":"2010-08-10T20:44:07Z","timestamp":1281473047000},"page":"121-130","source":"Crossref","is-referenced-by-count":9,"title":["Energy-efficient fault tolerance in chip multiprocessors using Critical Value Forwarding"],"prefix":"10.1109","author":[{"given":"Pramod","family":"Subramanyan","sequence":"first","affiliation":[]},{"given":"Virendra","family":"Singh","sequence":"additional","affiliation":[]},{"given":"Kewal K.","family":"Saluja","sequence":"additional","affiliation":[]},{"given":"Erik","family":"Larsson","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003565"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2001.903262"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/378993.379247"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5457061"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859631"},{"key":"ref11","first-page":"213","article-title":"Paceline: Improving Single-Thread Performance in Nanoscale CMPs through Core Overclocking","author":"greskamp","year":"2007","journal-title":"Proc 16th PACT"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.8"},{"key":"ref13","first-page":"123","article-title":"System level analysis of fast, per-core DVFS using on-chip switching regulators","author":"kim","year":"2008","journal-title":"Proceedings of the 14th HPCA"},{"journal-title":"Fault Tolerant Systems","year":"2007","author":"koren","key":"ref14"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2008.4658656"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2005.15"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2007.1090"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.23"},{"key":"ref19","first-page":"99","article-title":"Detailed Design and Evaluation of Redundant Multithreading Alternatives","author":"mukherjee","year":"2002","journal-title":"Proc of 29th ISCA"},{"key":"ref28","article-title":"Power-Efficient Redundant Execution for Chip Multiprocessors","author":"subramanyan","year":"2009","journal-title":"Proceedings of 3rd WDSN"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2005.70"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.42"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1999.809458"},{"key":"ref6","first-page":"83","article-title":"Wattch: a framework for architectural-level power analysis and optimizations","author":"brooks","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/1785481.1785516"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.110"},{"journal-title":"SESC Simulator","year":"2005","author":"renau","key":"ref8"},{"key":"ref7","article-title":"OpenSPARC: An Open Platform for Hardware Reliability Experimentation","author":"parulkar","year":"2008","journal-title":"IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE)"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2008.107"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771800"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250720"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2005.20"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/FTCS.1999.781037"},{"key":"ref21","first-page":"25","article-title":"Transient Fault Detection via Simultaneous Multithreading","author":"reinhardt","year":"2002","journal-title":"Proceedings of the 27th ISCA"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605403"},{"key":"ref23","article-title":"CACTI 5.1","author":"thoziyoor","year":"2008","journal-title":"Technical Report HPL-2008-20"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/1024393.1024420"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2002.1028924"}],"event":{"name":"Networks (DSN)","start":{"date-parts":[[2010,6,28]]},"location":"Chicago, IL, USA","end":{"date-parts":[[2010,7,1]]}},"container-title":["2010 IEEE\/IFIP International Conference on Dependable Systems & Networks (DSN)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5532324\/5544245\/05544918.pdf?arnumber=5544918","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,18]],"date-time":"2017-03-18T22:14:41Z","timestamp":1489875281000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5544918\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,6]]},"references-count":33,"URL":"https:\/\/doi.org\/10.1109\/dsn.2010.5544918","relation":{},"subject":[],"published":{"date-parts":[[2010,6]]}}}