{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,21]],"date-time":"2026-02-21T19:56:51Z","timestamp":1771703811768,"version":"3.50.1"},"reference-count":40,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,6]]},"DOI":"10.1109\/dsn.2012.6263951","type":"proceedings-article","created":{"date-parts":[[2012,8,16]],"date-time":"2012-08-16T16:04:08Z","timestamp":1345133048000},"page":"1-11","source":"Crossref","is-referenced-by-count":60,"title":["VARIUS-NTV: A microarchitectural model to capture the increased sensitivity of manycores to process variations at near-threshold voltages"],"prefix":"10.1109","author":[{"given":"Ulya R.","family":"Karpuzcu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Krishna B.","family":"Kolluru","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nam Sung","family":"Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Josep","family":"Torrellas","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2005.1609253"},{"key":"35","article-title":"Quantifying the impact of process variability on microprocessor behavior","author":"romanescu","year":"2006","journal-title":"Workshop on Architectural Reliability"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2005.82"},{"key":"36","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669170"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391550"},{"key":"33","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749712"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-2283-6_7"},{"key":"34","author":"renau","year":"2005","journal-title":"SESC Simulator"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253179"},{"key":"39","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.40"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2034764"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/92.645062"},{"key":"37","doi-asserted-by":"publisher","DOI":"10.1109\/TSM.2007.913186"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2080550"},{"key":"38","author":"srivastava","year":"2005","journal-title":"Statistical Analysis and Optimization for VLSI Timing and Power"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2006.4271854"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1145\/566408.566414"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2007.364539"},{"key":"40","year":"0","journal-title":"The R Project for Statistical Computing"},{"key":"22","year":"2009","journal-title":"International Technology Roadmap for Semiconductors (ITRS)"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2006.1598114"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"25","article-title":"Mitigating the impact of process variations on processor register files and execution units","author":"liang","year":"2006","journal-title":"International Symposium on Microarchitecture"},{"key":"26","doi-asserted-by":"publisher","DOI":"10.1145\/1065010.1065034"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2005.193764"},{"key":"28","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2035453"},{"key":"29","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2007.4342741"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775920"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1147\/rd.504.0433"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1974.1050511"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416630"},{"key":"30","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.852295"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2035451"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.895613"},{"key":"32","year":"0","journal-title":"Predictive Technology Model (PTM)"},{"key":"5","year":"0","journal-title":"BSIM"},{"key":"31","doi-asserted-by":"publisher","DOI":"10.1109\/66.806117"},{"key":"4","first-page":"218","article-title":"A physical alpha-power law MOSFET model","author":"bowman","year":"1999","journal-title":"Proceedings 1999 International Symposium on Low Power Electronics and Design (Cat No 99TH8477) LPE"},{"key":"9","author":"cheng","year":"1999","journal-title":"MOSFET Modeling and BSIM3 User's Guide"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.917509"}],"event":{"name":"2012 42nd Annual IEEE\/IFIP International Conference on Dependable Systems and Networks (DSN)","location":"Boston, MA, USA","start":{"date-parts":[[2012,6,25]]},"end":{"date-parts":[[2012,6,28]]}},"container-title":["IEEE\/IFIP International Conference on Dependable Systems and Networks (DSN 2012)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6253623\/6263904\/06263951.pdf?arnumber=6263951","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T16:17:14Z","timestamp":1490113034000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6263951\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,6]]},"references-count":40,"URL":"https:\/\/doi.org\/10.1109\/dsn.2012.6263951","relation":{},"subject":[],"published":{"date-parts":[[2012,6]]}}}