{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T10:58:06Z","timestamp":1725447486129},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,6]]},"DOI":"10.1109\/dsnw.2010.5542606","type":"proceedings-article","created":{"date-parts":[[2010,8,10]],"date-time":"2010-08-10T20:22:40Z","timestamp":1281471760000},"page":"131-135","source":"Crossref","is-referenced-by-count":2,"title":["Fault tolerant communication in 3D integrated systems"],"prefix":"10.1109","author":[{"given":"Vladimir","family":"Pasca","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lorena","family":"Anghel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mounir","family":"Benabdenbi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","article-title":"Examination of Delay and Signal Integrity Metrics in Through Silicon Vias. 3D Integration Workshop","author":"grange","year":"2009","journal-title":"DATE conference"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.1109\/TVLSI.2005.848816"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1109\/TCAD.2005.847907"},{"key":"ref13","article-title":"A New Framework for Analyzing Test Generation and Diagnosis Algorithms for Board Interconnects","author":"jarwala","year":"1989","journal-title":"IEEE International Test Conference"},{"year":"2004","author":"lin","journal-title":"Error Control Coding Fundamentals and Applications","key":"ref14"},{"key":"ref15","article-title":"Turbo Product Code","author":"williams","year":"0","journal-title":"IEEE 802 16 Tutorial Presentations"},{"year":"2007","author":"koren","journal-title":"Fault Tolerant Systems","key":"ref16"},{"key":"ref4","article-title":"Factors affecting copper filling process within high aspect ratio deep vias for 3D chip stacking","author":"kim","year":"2006","journal-title":"Proc 56th Electronic Components and Technology Conf"},{"key":"ref3","article-title":"Three-dimension integrated circuit designs","author":"friedman","year":"2008","journal-title":"Morgan Faufman (System on Silicon Series)"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1109\/IITC.2007.382392"},{"key":"ref5","article-title":"Failure mechanisms and optimum design for electroplated copper Through-Silicon Vias (TSV)","author":"liu","year":"2009","journal-title":"Proc 59th Electron Components Technol Conf"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1109\/ICCAD.2008.4681638"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1109\/DFTVS.2003.1250092"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1109\/ECTC.2008.4550025"},{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1147\/rd.504.0491"},{"year":"0","journal-title":"Interconnects","key":"ref9"}],"event":{"name":"2010 International Conference on Dependable Systems and Networks Workshops (DSN-W)","start":{"date-parts":[[2010,6,28]]},"location":"Chicago, IL, USA","end":{"date-parts":[[2010,7,1]]}},"container-title":["2010 International Conference on Dependable Systems and Networks Workshops (DSN-W)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5532085\/5542594\/05542606.pdf?arnumber=5542606","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,10,14]],"date-time":"2020-10-14T15:05:56Z","timestamp":1602687956000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/5542606"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,6]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/dsnw.2010.5542606","relation":{},"subject":[],"published":{"date-parts":[[2010,6]]}}}