{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T04:47:34Z","timestamp":1729658854822,"version":"3.28.0"},"reference-count":31,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,6]]},"DOI":"10.1109\/dsnw.2010.5542612","type":"proceedings-article","created":{"date-parts":[[2010,8,10]],"date-time":"2010-08-10T20:22:40Z","timestamp":1281471760000},"page":"95-100","source":"Crossref","is-referenced-by-count":8,"title":["Massive statistical process variations: A grand challenge for testing nanoelectronic circuits"],"prefix":"10.1109","author":[{"given":"B.","family":"Becker","sequence":"first","affiliation":[{"name":"University of Freiburg, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S.","family":"Hellebrand","sequence":"additional","affiliation":[{"name":"University of Paderborn, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"I.","family":"Polian","sequence":"additional","affiliation":[{"name":"University of Passau, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"B.","family":"Straube","sequence":"additional","affiliation":[{"name":"Fraunhofer IIS\/EAS, Dresden, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"W.","family":"Vermeiren","sequence":"additional","affiliation":[{"name":"Fraunhofer IIS\/EAS, Dresden, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"H.-J.","family":"Wunderlich","sequence":"additional","affiliation":[{"name":"University of Stuttgart, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687480"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1007\/BF00993090"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2009.5196027"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2021728"},{"journal-title":"ITC'99 Benchmarks Benchmark information and circuits","year":"0","key":"ref12"},{"key":"ref13","first-page":"694","article-title":"On delay fault testing in logic circuits","volume":"5","author":"lin","year":"1987","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.811442"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/12.494102"},{"key":"ref16","doi-asserted-by":"crossref","first-page":"941","DOI":"10.1145\/1403375.1403603","article-title":"Globally Optimized Robust Systems to Overcome Scaled CMOS Reliability Challenges","author":"mitra","year":"2008","journal-title":"Proceedings Design Automation and Test in Europe"},{"journal-title":"Nangate 45nm open cell library","year":"0","key":"ref17"},{"key":"ref18","doi-asserted-by":"crossref","first-page":"7","DOI":"10.1023\/A:1008244815697","article-title":"On-line testing for VLSI—a compendium of approaches","volume":"12","author":"nicolaidis","year":"1998","journal-title":"J Electronic Testing"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2007.4437666"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1630004"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.110"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2006.145"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TIM.2003.818736"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.923107"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2008.4700627"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/s10766-009-0124-7"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2008.4479838"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2004.85"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.69"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2008.32"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TSM.2007.913191"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1007\/11499107_17"},{"key":"ref22","doi-asserted-by":"crossref","first-page":"1402","DOI":"10.1145\/1403375.1403715","article-title":"Variation tolerant NoC design by means of self-calibrating links","author":"simone","year":"2008","journal-title":"Proceedings Design Automation and Test in Europe"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090907"},{"journal-title":"Statistical Analysis and Optimization for VLSI Timing and Power","year":"2005","author":"srivastava","key":"ref24"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1978.1675139"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/SECON.1999.766130"},{"key":"ref25","first-page":"205","article-title":"Analogue fault simulation by aFSIM","author":"straube","year":"2000","journal-title":"Design Automation and Test in Europe Conference and Exhibition DATE 2000—User Forum"}],"event":{"name":"2010 International Conference on Dependable Systems and Networks Workshops (DSN-W)","start":{"date-parts":[[2010,6,28]]},"location":"Chicago, IL, USA","end":{"date-parts":[[2010,7,1]]}},"container-title":["2010 International Conference on Dependable Systems and Networks Workshops (DSN-W)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5532085\/5542594\/05542612.pdf?arnumber=5542612","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,4]],"date-time":"2021-11-04T13:49:01Z","timestamp":1636033741000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/5542612\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,6]]},"references-count":31,"URL":"https:\/\/doi.org\/10.1109\/dsnw.2010.5542612","relation":{},"subject":[],"published":{"date-parts":[[2010,6]]}}}