{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T16:03:27Z","timestamp":1761581007525,"version":"3.28.0"},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,5]]},"DOI":"10.1109\/dtis.2012.6232957","type":"proceedings-article","created":{"date-parts":[[2012,7,19]],"date-time":"2012-07-19T19:41:56Z","timestamp":1342726916000},"page":"1-6","source":"Crossref","is-referenced-by-count":3,"title":["Analytical dynamic power model for LUT based components"],"prefix":"10.1109","author":[{"given":"Chalbi","family":"Najoua","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Boubaker","family":"Mohamed","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bedoui Mohamed","family":"Hedi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1999.810662"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1145\/988952.988992"},{"journal-title":"Development Board User s Guide","year":"2003","key":"10"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2005307"},{"key":"7","first-page":"369","article-title":"Analytical high-level power model for LUTbased components","author":"jevtic","year":"2008","journal-title":"Proceedings of PATMOS"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2006.1692831"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.829819"},{"key":"4","first-page":"46","article-title":"High level power modeling of CPLDs and FPGA","author":"shang","year":"2001","journal-title":"Proceedings of International Conference on Computer Design"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1623\/hysj.49.6.1025.55720"},{"key":"8","doi-asserted-by":"crossref","first-page":"396","DOI":"10.1007\/978-3-540-48302-1_44","article-title":"Power modelling in field programmable gate arrays (FPGA","volume":"1673","author":"garcia","year":"1999","journal-title":"Lecture Notes in Computer Science Field Programmable Logic and Applications"},{"journal-title":"Pro X FPGA User Guide UG012","year":"2007","key":"11"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2015326"}],"event":{"name":"2012 7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","start":{"date-parts":[[2012,5,16]]},"location":"Tunis, Tunisia","end":{"date-parts":[[2012,5,18]]}},"container-title":["7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6225516\/6232941\/06232957.pdf?arnumber=6232957","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,20]],"date-time":"2017-06-20T17:37:49Z","timestamp":1497980269000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6232957\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,5]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/dtis.2012.6232957","relation":{},"subject":[],"published":{"date-parts":[[2012,5]]}}}